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NANO908-NB0AN Datasheet(PDF) 10 Page - Nuvoton Technology Corporation |
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NANO908-NB0AN Datasheet(HTML) 10 Page - Nuvoton Technology Corporation |
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10 / 160 page  NUMICRO® NANO100 (B) DATASHEET May 31, 2016 Page 10 of 160 Revision 1.08 2 FEATURES The equipped features are dependent on the product line and their sub products. 2.1 Nano100 Features – Base Line Core ARM ® Cortex™-M0 core running up to 42 MHz One 24-bit system timer Supports Low Power Sleep mode Single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Serial Wire Debug supports with 2 watchpoints/4 breakpoints Brown-out Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation Flash EPROM Memory Runs up to 42 MHz with zero wait state for discontinuous address read access 64K/32K/123K bytes application program memory (APROM) 4 KB in system programming (ISP) loader program memory (LDROM) Programmable data flash start address and memory size with 512 bytes page erase unit In System Program (ISP)/In Application Program (IAP) to update on-chip Flash EPROM SRAM Memory 16K/8K bytes embedded SRAM Supports DMA mode DMA: Supports 8 channels: one VDMA channel, 6 PDMA channels and one CRC channel VDMA Memory-to-memory transfer Supports block transfer with stride Supports word/half-word/byte boundary address Supports address direction: increment and decrement PDMA Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer Supports word boundary address Supports word alignment transfer length in memory-to-memory mode Supports word/half-word/byte alignment transfer length in peripheral-to- memory and memory-to-peripheral mode Supports word/half-word/byte transfer data width from/to peripheral |
Similar Part No. - NANO908-NB0AN |
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