PALCE22V10
USE ULTRA37000TM FOR
ALL NEW DESIGNS
Document #: 38-03027 Rev. *B
Page 6 of 13
tS1
Input or Feedback Set-Up Time
3
5
6
10
15
ns
tS2
Synchronous Preset Set-Up
Time
4
6
7
10
15
ns
tH
Input Hold Time
0
0
0
0
0
ns
tP
External Clock Period (tCO + tS)
7
10
12
20
30
ns
tWH
Clock Width HIGH[6]
2.5
3
3
6
13
ns
tWL
Clock Width LOW[6]
2.5
3
3
6
13
ns
fMAX1
External Maximum
Frequency (1/(tCO + tS))
[11]
143
100
76.9
55.5
33.3
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL))
[6, 12]
200
166
142
83.3
35.7
MHz
fMAX3
Internal Feedback Maximum
Frequency (1/(tCF + tS))
[6,13]
181
133
111
68.9
38.5
MHz
tCF
Register Clock to
Feedback Input[6,14]
2.5
2.5
3
4.5
13
ns
tAW
Asynchronous Reset Width
8
8
10
15
25
ns
tAR
Asynchronous Reset
Recovery Time
4
5
6
10
25
ns
tAP
Asynchronous Reset to
Registered Output Delay
7.5
12
13
20
25
ns
tSPR
Synchronous Preset
Recovery Time
4
6
8
10
15
ns
tPR
Power-up Reset Time[6,15]
1
1
1
1
1
µs
Military and Industrial Switching Characteristics PALCE22V10 [2, 7]
Parameter
Description
22V10-10
22V10-15
22V10-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tPD
Input to Output
Propagation Delay[8]
3
10
3
15
3
25
ns
tEA
Input to Output Enable Delay[9]
10
15
25
ns
tER
Input to Output Disable Delay[10]
10
15
25
ns
tCO
Clock to Output Delay[8]
2
7
2
8
2
15
ns
tS1
Input or Feedback Set-up Time
6
10
18
ns
tS2
Synchronous Preset Set-up Time
7
10
18
ns
tH
Input Hold Time
0
0
0
ns
tP
External Clock Period (tCO + tS)
12
20
33
ns
tWH
Clock Width HIGH[6]
3
6
14
ns
tWL
Clock Width LOW[6]
3
6
14
ns
fMAX1
External Maximum Frequency
(1/(tCO + tS))
[11]
76.9
50.0
30.3
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL))
[6, 12 ]
142
83.3
35.7
MHz
Notes:
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS.
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper
operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
Commercial Switching Characteristics PALCE22V10 (continued)[2, 7]
Parameter
Description
22V10-5
22V10-7
22V10-10
22V10-15
22V10-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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