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CY7C1062AV33 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. CY7C1062AV33
Description  The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits.
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1062AV33 Datasheet(HTML) 1 Page - Cypress Semiconductor

   
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512K x 32 Static RAM
CY7C1062AV33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-05137 Rev. *D
Revised February 21, 2003
Features
• High speed
—tAA = 8, 10, 12 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and CE3
features
Functional Description
The CY7C1062AV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
Writing to the device is accomplished by enabling the chip
(CE1, CE2 and CE3 LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (BA) is LOW, then data from I/O
pins (I/O0 through I/O7), is written into the location specified on
the address pins (A0 through A18). If Byte Enable B (BB) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23
and I/O24 to I/O31, respectively.
Reading from the device is accomplished by enabling the chip
(CE1, CE2, and CE3 LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (BA) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
Enable B (BB) is LOW, then data from memory will appear on
I/O8 to I/O15. Similarly, Bc and BD correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
The input/output pins (I/O0 through I/O31) are placed in a
high-impedance state when the device is deselected (CE1,
CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (BA-D HIGH), or during a write
operation (CE1, CE2, and CE3 LOW, and WE LOW).
The CY7C1062AV33 is available in a 119-ball pitch ball grid
array (PBGA) package.
Selection Guide
–8
–10
–12
Unit
Maximum Access Time
810
12
ns
Maximum Operating Current
Com’l
300
275
260
mA
Ind’l
300
275
260
Maximum CMOS Standby Current
Com’l/Ind’l50
50
50
mA
Logic Block Diagram
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
COLUMN
DECODER
INPUT BUFFERS
512K x 32
ARRAY
A 0
4096 x 4096
I/O0–I/O31
OE
CE3
BA
BD
A 9
BB
BC
WE
CE2
CE1


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