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ZL50012/QCC Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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ZL50012/QCC Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
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10 / 65 page  ZL50012 Data Sheet 13 Zarlink Semiconductor Inc. 44 A2 FPo2 ST-BUS Frame Pulse Output 2 (5V Tolerant High Speed Three-state Output): ST-BUS frame pulse output which stays low for 30 ns or 61 ns at the frame boundary. Its frequency is 8 KHz. The polarity of this signal can be changed using the Internal Mode Selection register. 45 B1 CKo2 ST-BUS Clock Output 2 (5 V Tolerant High Speed Three- state Output): A 32.768 MHz or 16.384 MHz clock output. The clock falling edge defines the output frame boundary. The polarity of this signal can be changed using the Internal Mode Selection register. 46 A1 ODE Output Drive Enable (5 V Tolerant Input): This is the asynchronously output enable control for the STo0 - 15 and the output driven high control for the STOHZ 0 - 15 serial outputs. When it is high, the STo0 - 15 and STOHZ 0 - 15 are enabled. When it is low, the STo0 - 15 are in the high impedance state and the STOHZ 0 - 15 are driven high. 49 - 52 59 - 62 69 - 72 83 - 86 D2, C2, C1, D1 E2, E1, F1, F2 H3, H1, H2, J1 L2, L3, M1, K3 STo0 - 3 STo4 - 7 STo8 - 11 STo12 - 15 Serial Output Streams 0 to 15 (5 V Tolerant Three-state Outputs): The data rate of these output streams can be selected independently using the stream control output registers. In the 2.048 Mb/s mode, these pins have serial TDM data streams at 2.048 Mb/s with 32 channels per stream. In the 4.096 Mb/s mode, these pins have serial TDM data streams at 4.096 Mb/s with 64 channels per stream. In the 8.192 Mb/s mode, these pins have serial TDM data streams at 8.192 Mb/s with 128 channels per stream. 53 - 56 63 - 66 73 - 76 87 - 90 C3, D3, E4, E3 F3, G3, G1, G2 J3, K1, L1, J2 M2, K4, M3, K2 STOHZ 0 - 3 STOHZ 4 - 7 STOHZ 8 - 11 STOHZ 12 - 15 Serial Output Streams High Impedance Control 0 to 15 (5 V Tolerant Three-state Outputs): These pins are used to enable (or disable) external three-state buffers. When a output channel is in the high impedance state, the STOHZ drives high for the duration of the corresponding output channel. When the STo channel is active, the STOHZ drives low for the duration of the corresponding output channel. 93 - 96 97 - 100 103 - 106 107 - 110 M4, K5, J5, L4 L6, K6, M6, L7 M7, M8, K8, K9 L8, M9, L9, L5 D0 - D3 D4 - D7 D8 - D11 D12 - D15 Data Bus 0 - 15 (5 V Tolerant I/Os): These pins form the 16-bit data bus of the microprocessor port. 111 M5 DTA Data Transfer Acknowledgment (5 V Tolerant Three-state Output): This active low output indicates that a data bus transfer is complete. A pull-up resistor is required to hold this pin at HIGH level. 114 K7 CS Chip Select (5 V Tolerant Input): Active low input used by the microprocessor to enable the microprocessor port access. Pin Description (continued) LQFP Pin Number LBGA Ball Number Name Description |
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