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K9F1G08U0E Datasheet(PDF) 12 Page - Samsung semiconductor

Part No. K9F1G08U0E
Description  1Gb E-die NAND Flash
Download  38 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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K9F1G08U0E Datasheet(HTML) 12 Page - Samsung semiconductor

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K9F1G08U0E
FLASH MEMORY
Rev. 1.11
SAMSUNG CONFIDENTIAL
2.4 Valid Block
NOTE :
1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both
cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the
attached technical notes for appropriate management of invalid blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.
2.5 AC Test Condition
(K9F1G08U0E-XCB0 :TA=0 to 70
C, K9F1G08U0E-XIB0:TA=-40 to 85C, K9F1G08U0E : Vcc=2.7V~3.6V unless otherwise noted)
2.6 Capacitance(TA=25C, VCC=3.3V, f=1.0MHz)
NOTE :
Capacitance is periodically sampled and not 100% tested.
2.7 Mode Selection
NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.
Parameter
Symbol
Min
Typ.
Max
Unit
K9F1G08U0E
NVB
1,004
-
1,024
Blocks
Parameter
K9F1G08U0E
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL=50pF
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
CLE
ALE
CE
WE
RE
WP
Mode
HL
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input(4clock)
HL
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input(4clock)
LLL
H
H
Data Input
LLL
H
X
Data Output
X
X
X
X
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
L
Write Protect
XX
H
X
X
0V/VCC(2)
Stand-by


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