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K9F1G08U0E Datasheet(PDF) 9 Page - Samsung semiconductor |
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K9F1G08U0E Datasheet(HTML) 9 Page - Samsung semiconductor |
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9 / 38 page 
- 9 - datasheet K9F1G08U0E FLASH MEMORY Rev. 1.11 SAMSUNG CONFIDENTIAL [Figure 1] K9F1G08U0E Functional Block Diagram [Figure 2] K9F1G08U0E Array Organization NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A8 A9 A10 A11 *L *L *L *L 3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19 4th Cycle A20 A21 A22 A23 A24 A25 A26 A27 VCC X-Buffers Command I/O Buffers & Latches Latches & Decoders Y-Buffers Latches & Decoders Register Control Logic & High Voltage Generator Global Buffers Output Driver VSS A12 - A27 A0 - A11 Command CE RE WE CLE WP I/0 0 I/0 7 VCC VSS ALE 1,024M + 32M Bit NAND Flash ARRAY (2,048 + 64)Byte x 65,536 Y-Gating Data Register & S/A 2K Bytes 64 Bytes 64K Pages (=1,024 Blocks) 2K Bytes 8 bit 64 Bytes 1 Block = 64 Pages (128K + 4k) Byte I/O 0 ~ I/O 7 1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 1,024 Blocks = 1,056 Mbits Page Register Row Address Row Address Column Address Column Address |
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