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CSE7759B Datasheet(PDF) 19 Page - Core Technology (Shenzhen) Co., Ltd. |
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CSE7759B Datasheet(HTML) 19 Page - Core Technology (Shenzhen) Co., Ltd. |
19 / 25 page 本资料为芯海科技专有财产,非经许可,不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯.成浩瀚之海 19/25 Table 3-5 Address Data Storage 3nFH (Calibration voltage cycle* calibration voltage) high 8bit 3nEH (Calibration voltage cycle* calibration voltage) medium 8bit 3nDH (Calibration voltage cycle* calibration voltage) low 8bit 3nCH (Calibration current cycle* calibration current) high 8bit 3nBH (Calibration current cycle* calibration current) medium 8bit 3nAH (Calibration current cycle* calibration current) low 8bit 3n9H (Calibration power cycle* calibration power) high 8bit 3n8H (Calibration power cycle* calibration power) medium 8bit 3n7H (Calibration power cycle* calibration power) low 8bit 3n6H Reserved 3n5H Reserved 3n4H Reserved 3n3H Reserved 3n2H Reserved 3n1H Reserved 3n0H Checksum2, 8bit Note: Checksum2 = Sum of 3n7H~3nFH data; lowering by 8 bits. ◆Adj.bit2~bit0 (calibration times) calibration address selection: Table 3-6 2 Bit 1 Bit 0 Bit Remarks 0 0 0 n=F 0 0 1 n=E 0 1 0 n=D 0 1 1 n=C 1 0 0 n=B 1 0 1 n=A |
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