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Confidential

SiFirst_DS_1565_V1.2

SF1565

Block Diagram

RT

5

CS

6

FB

2

Slope

compensation

OSC

Q

Q

SET

CLR

S

R

OCP

& Compensation

PWM

&

Logic

Soft start

CS Floating

Protection

RI short/floating

protection

Green Mode

operation

VIN

3

UVLO

POR

5.9V

RI

4

Trimmed Voltage &

Current Reference

GATE

Soft Gate

Driver

8

VDD

7

82ms Delay

4.4V

1

70uA

1.065V

Frequency Shuffling

LEB

Burst Mode

Control

33V

25V

OVP

OTP

OLP

GND

Pin Description

Pin Num

Pin Name

I/O

Description

1

GND

P

IC ground pin.

2

FB

I

Voltage feedback pin. The loop regulation is achieved by connecting a

photo-coupler to this pin. PWM duty cycle is generated by this pin voltage

and the current sense signal at Pin 6.

3

VIN

I

This pin is connected to the rectified line input via a large value resistor.

The function of the pin is for startup and line voltage sensing.

4

RI

I

Set the switching frequency by connecting a resistor between RI and

GND. This pin has floating/short-to-GND protection.

5

RT

I

This pin is for over temperature protection by connecting an external NTC

resistor to ground. Once the pin voltage drops below a fixed limit of

1.065V, PWM output will be disabled.

6

CS

I

Current sense input pin.

7

VDD

P

IC power supply pin.

8

GATE

O

Totem-pole gate driver output to drive the external MOSFET.

Parameter

Value

Unit

VDD/VIN DC Supply Voltage

33

V

VDD DC Clamp Current

10

mA