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RTL8211E-VL-CG Datasheet(PDF) 71 Page - Realtek Semiconductor Corp. |
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RTL8211E-VL-CG Datasheet(HTML) 71 Page - Realtek Semiconductor Corp. |
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RTL8211E/RTL8211EG Datasheet Integrated 10/100/1000M Ethernet Transceiver 63 Track ID: JATR-2265-11 Rev. 1.4 Table 59. RGMII Timing Parameters Symbol Description Min Typical Max Units TGCC Clock Cycle Duration (Giga) 7.2 8 8.8 ns Clock Cycle Duration (100Mbps) 36 40 44 ns Clock Cycle Duration (10Mbps) 360 400 440 ns Duty_G Duty Cycle for Gigabit 45 50 55 % Duty_T Duty Cycle for 10/100T 40 50 60 % tR RXC Rise Time (20%~80%) - - 0.75 ns tF RXC Fall Time (20%~80%) - - 0.75 ns TsetupT Data to Clock Output Setup (at transmitter integrated delay) 1.2 2 - ns TholdT Data to Clock Output Hold (at transmitter integrated delay) 1.2 2 - ns TsetupR Data to Clock Input Setup (at receiver integrated delay) 1.0 2 - ns TholdR Data to Clock Input Hold (at receiver integrated delay) 1.0 2 - ns TskewT Data to Clock Output Skew (at transmitter) -0.5 0 0.5 ns TskewR Data to Clock Input Skew (at receiver) This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5ns and less than 2.0ns will be added to the associated clock signal. 1 1.8 2.6 ns |
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