[Figure 13] Read ID Operation

[Figure 14] RESET Operation

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datasheet

FLASH MEMORY

Rev. 1.1

K9F1G08U0D

5.6 Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles

sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID

mode until further commands are issued to it. Figure 13 shows the operation sequence.

5.7 Reset

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or

erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially

programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high.

If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the

Reset command is written. Refer to Figure 14 below

[Table 3] Device Status

Device

Device Code (2nd Cycle)

3rd Cycle

4th Cycle

5th Cycle

K9F1G08U0D

F1h

00h

95h

40h

After Power-up

After Reset

Operation mode Mode

00h Command is latched

Waiting for next command

CE

CLE

ALE

RE

WE

90h

00h

Device

4th Cyc.

Code

ECh

3rd Cyc.

5th Cyc.

FFh

R/B