AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 8 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
B0,1 A10/AP A12-11,A9-0
Note
Register
Mode Register Set
H
X
L
L
L
L
X
1, 2
Auto Refresh
H
H
L
L
L
H
X
X
3
Refresh
Self
Entry
L
3
Refresh
Exit
L
H
L
H
H
H
X
X
3
H
XXX
3
Bank Active & Row Address
H
X
L
L
H
H
X
V
Row Address
Read &
Auto Precharge Disable
L
Column
4
Column Address Auto Precharge Enable HX
L
H
L
H
X
V
H
Address
4, 5
(A0-A9)
Write &
Auto Precharge Disable
L
Column
4
Column Address Auto Precharge Enable
HX
L
H
L
L
X
V
H
Address
4, 5
(A0-A9)
Burst Stop
H
X
L
H
H
L
X
X
6
Precharge
Bank Selection
H
X
L
L
H
L
X
V
L
All Banks
XH
Clock Suspend or
Entry
H
L
H
X
X
X
X
Active Power Down
L
V
V
V
X
L
H
X
XXX
X
Precharge Power Down
Entry
H
L
H
X
X
X
X
Mode
L
H
H
H
X
Exit
L
H
H
X
X
X
X
L
VVV
DQM
H
X
V
X
7
No Operation Command
H
X
H
X
X
X
X
X
L
HHH
OP CODE
X
Exit
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note: 1.
OP Code: Operand Code
A0 - A12, BA0 - BA1: Program keys. (@MRS)
2.
MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3.
Auto refresh functions are same as CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4.
BA0 - BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
5.
During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.
Burst stop command is valid at every burst length.
7.
DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)