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Data Acquisition Microcontroller
XE88LC05
7
D0109-40
5 Memory organization
The CPU uses a Harvard architecture, so that memory is organized in two separated fields:
program memory and data memory. As both memories are separated, the central processing
unit can read/write data at the same time it loads an instruction. Peripherals and system control
registers are mapped on data memory space.
Program memory is made in one page. Data is made of several 256 bytes pages.
5.1 Program memory
The program memory is implemented as Multiple Time Programmable (MTP) Flash memory
or ROM. The power consumption of MTP memory is linear with the access frequency (no sig-
nificant static current).
Size of the MTP Flash memory is 8192 x 22 bits (= 22 kBytes)
Size of the ROM memory is 6144 x 22 bits (= 17 kBytes)
5.2 Data memory
The data memory is implemented as static Random-Access Memory (RAM). The RAM size is
512 x 8 bits plus 8 low power RAM bytes that require very low current when addressed. Pro-
grams using the low-power RAM instead of RAM will use even less current.
block
size
address
MTP
8192 x 22
H0000 - H1FFF
ROM
6144 x 22
H0000 - H1BFF
Table 5.1:
Program addresses for MTP or ROM memory
block
size
address
LP RAM
8 x 8
H0000 - H0007
RAM
512 x 8
H0080 - H027F
Table 5.2:
RAM addresses
Figure 5.1:
Memory organization
CPU
Program
memory
LP RAM
Peripherals
RAM
22 bits wide
8 bits wide
CPU
registers
Instruction
pipeline
8k instructions MTP
512 Bytes
0h0000
0h1FFF / 01hBFF
0h0000
0h0010
0h0080
0h027F
or
6k instructions ROM
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