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CY28405OXC Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY28405OXC
Description  CK409-Compliant Clock Synthesizer
Download  19 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY28405OXC Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY28405
Document #: 38-07512 Rev. *B
Page 9 of 19
Byte 11: Control Register 11
Bit
@Pup
Name
Description
7
0
Reserved
Vendor Test Mode (always program to 0)
6
0
Recovery_Frequency
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use Hardware settings
1: Use Last SW table Programmed values
5
0
Watchdog Time Stamp
Reload
To enable this function the register bit must first be set to “0” before toggling
to “1”.
0: Do not reload
1: Reset timer but continue to count.
4
0
WD_Alarm
This bit is set to “1” when the Watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp
3
0
WD_TIMER3
Watchdog timer time stamp selection:
0000: Off
0001: 2 second
0010: 4 seconds
0011: 6 seconds
.
.
.
1110: 28seconds
1111: 30seconds
2
0
WD_TIMER2
10
WD_TIMER1
0
0
WD_TIMER0
Byte 12: Control Register 12
Bit
@Pup
Name
Description
7
0
CPU_FSEL_N8
If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[8:0] and
CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
6
0
CPU_FSEL_N7
5
0
CPU_FSEL_N6
4
0
CPU_FSEL_N5
3
0
CPU_FSEL_N4
2
0
CPU_FSEL_N3
1
0
CPU_FSEL_N2
0
0
CPU_FSEL_N1
Byte 13: Control Register 13
Bit
@Pup
Name
Description
7
0
CPU_FSEL_N0
If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[8:0] and
CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
60
CPU_FSEL_M6
50
CPU_FSEL_M5
40
CPU_FSEL_M4
30
CPU_FSEL_M3
20
CPU_FSEL_M2
10
CPU_FSEL_M1
00
CPU_FSEL_M0
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
0
FS_(E:A)
FS_Override
0 = Select operating frequency by FS(E:A) input pins
1 = Select operating frequency by FSEL(4:0) settings
6
1
Reserved
Reserved, Set = 1
5
0
Reserved
Reserved, Set = 0


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