256 Kb (64K x 4) Static RAM
CY7C194B
CY7C195B
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05409 Rev. *A
Revised September 17, 2003
Features
• Fast access time: 12 ns, 15 ns, and 25 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Available in 24 DIP, 24 SOJ, 28 DIP, and 28 SOJ
General Description1
The CY7C194B-CY7C195B is a high-performance CMOS
Asynchronous SRAM organized as 64K × 4 bits that supports
an asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected. Output enable (OE) is
supported only in CY7C195B.2
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C194B-CY7C195B is available in 24 DIP, 24 SOJ, 28
DIP, and 28 SOJ package(s).
Notes:
Notes:
1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. All OE-specific descriptions and parameters in this datasheet pertain to CY7C195 only.
RAM Array
Column Decoder
Input Buffer
A
X
Power
Down
Circuit
I/Ox
OE
WE
CE
X
(7C195 only)
Logic Block Diagram
Product Portfolio
12 ns
15 ns
25 ns
Unit
Maximum Access Time
12
15
25
ns
Maximum Operating Current
90
80
80
mA
Maximum CMOS Standby Current
10
10
10
mA
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