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M48Z12-150PC1 Datasheet(PDF) 8 Page - STMicroelectronics

Part # M48Z12-150PC1
Description  5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M48Z12-150PC1 Datasheet(HTML) 8 Page - STMicroelectronics

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M48Z02, M48Z12
8/16
WRITE Mode
The M48Z02/12 is in the WRITE Mode whenever
W and E are active. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid tD-
VWH prior to the end of WRITE and remain valid for
tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
Figure 7. WRITE Enable Controlled, WRITE AC Waveform
Figure 8. Chip Enable Controlled, WRITE AC Waveforms
AI01331
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A10
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI01332B
tAVAV
tEHAX
tDVEH
A0-A10
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tAVWL
tELEH
tEHDX
DATA INPUT


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