CY28401
Document #: 38-07592 Rev. **
Page 2 of 14
Serial Data Interface
To enhance the flexibility and function of the clock buffer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initializes to
their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for
power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
Pin Description
Pin
Name
Type
Description
4,5
SRCT_IN, SRCC_IN
I,DIF
0.7V Differential SRC inputs from the clock synthesizer
8,9,12,13,16,17,20,21,29,30,
33,34,37,38,41,42
DIFT/C(7:0)
O,DIF 0.7V Differential Clock Outputs
6,7,14,15,35,36,43,44
OE_(7:0)
I,SE
3.3V LVTTL active low input for three-stating differential
outputs
28
HIGH_BW#
I,SE
3.3V LVTTL input for selecting PLL bandwidth
45
LOCK
O,SE 3.3V LVTTL output, transitions high when PL lock is
achieved (latched output)
26
PWRDWN#
I,SE
3.3V LVTTL input for Power Down, active low
1
SRC_DIV/2#
I,SE
3.3V LVTTL input for selecting input frequency divided by
two, active low
27
SRC_STOP#
I,SE
3.3V LVTTL input for SRC_Stop#, active low
23
SCLK
I,SE
SMBus Slave Clock Input
24
SDATA
I/O,OC Open collector SMBus data
46
IREF
I
A precision resistor is attached to this pin to set the differ-
ential output current
22
PLL/BYPASS#
I
3.3V LVTTL input for selecting fan-out or PLL operation
48
VDD_A
3.3V
3.3V Power Supply for PLL
47
VSS_A
GND
Ground for PLL
3,10,18,25,32,40
VSS
I
Ground for outputs
2,11,19,31,39
VDD
I
3.3V power supply for outputs
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation
1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
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