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CY24142
Document #: 38-07532 Rev. *B
Page 2 of 7
Layout Recommendations
The XIN and XOUT traces and pads as well as the crystal
should be placed away from any clock traces or noise sources.
Noise coupling into the XIN and XOUT traces may cause
start-up problems. A pad for a resistor to ground should be laid
out on the XOUT trace to be stuffed if necessary, in case
start-up issues occur.
Pin Description
Pin Name
Pin Number
Pin Description
XIN
1
Crystal Input.
VDD
2
Voltage Supply.
AVDD
3
Analog Voltage Supply.
OE1
4
Output Enable 1, 0 = CLK 2 and CLK3 off, 1 = CLK 2 and CLK3 on; weak internal
pull-down.
AVSS
5
Analog Ground.
VSSL
6
VDDL Ground.
NC
7
No Connect; leave floating.
CLK1
8
13.5-MHz Clock Output.
CLK2
9
54-MHz Clock Output; controlled by OE1.
OE2
10
Output Enable 2, 0 = CLK4 off, 1 = CLK4 on; weak internal pull-down.
VDDL
11
Voltage Supply.
NC
12
No Connect; leave floating.
VSS
13
Ground.
CLK3
14
18.432-MHz Buffered Reference Output, controlled by OE1.
CLK4
15
18.432-MHz Buffered Reference Output, controlled by OE2.
XOUT
16
Crystal Output.
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