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SY100EP195V Datasheet(PDF) 15 Page - Micrel Semiconductor

Part # SY100EP195V
Description  3.3V/5V 2.5GHz PROGRAMMABLE DELAY CHIP
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY100EP195V Datasheet(HTML) 15 Page - Micrel Semiconductor

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15
ECL Pro®
SY100EP195V
Micrel
M0643-121504
For best performance, use good high frequency layout
techniques, filter VCC supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the
SY100EP195V data inputs and outputs.
VBB Supply
The VBB pin is an internally generated supply, and is
available for use only by the SY100EP195V. When unused,
this pin should be left unconnected. The two common uses
for VBB are to handle a single-ended PECL input, and to re-
bias inputs for AC-coupling applications.
If IN, /IN is driven by a single-ended output, VBB is used
to bias the unused input. Please refer to Figures 7. The
PECL signal driving SY100EP195V may optionally be
inverted in this case.
When the signal is AC-coupled, VBB is used, as shown
in Figure 8, to re-bias IN, /IN. This ensures that
SY100EP195V inputs are within its acceptable common
mode range.
In all cases, VBB current sinking our sourcing must be
limited to 0.5mA or less.
APPLICATIONS INFORMATION
IN
/IN
Q
/Q
IN
/IN
Q
/Q
D[9:0]
SY100EP195V
SY100EP195V
#2
#1
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (11bits)
Figure 10a. Cascading Two SY100EP195V
IN
/IN
Q
/Q
IN
/IN
Q
/Q
SY100EP195V
SY100EP195V
#3
#2
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[11]
IN
/IN
Q
/Q
D[9:0]
SY100EP195V
#1
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (12bits)
Figure 10b. Cascading Three SY100EP195V
Setting D Input Logic Thresholds
As explained earlier, in all designs where the
SY100EP195V VEE supply is at zero volts, the D inputs
may accommodate CMOS and TTL level signals, as well as
PECL or LVPECL. Figures 9 show how to connect VCF and
VEF for all possible cases.
Cascading
Two or more SY100EP195V may be cascaded, in order
to extend the range of delays permitted. Each additional
SY100EP195V adds about 2200ps to the minimum delay,
and adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY100EP195V. Using this internal circuitry, SY100EP195V
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY100EP195V appear
in Figures 10. Table 7 lists the nominal delay for all the
cases that appear in Figures 10.


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