DP83816AVNG datasheet(7/105 Pages) NSC

Part #	DP83816AVNG

Description	DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPHYTER-II)

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Manufacturer	NSC [National Semiconductor (TI)]

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2.0 Pin Description (Continued)

Note: MII is normally in TRI-STATE, unless enabled by CFG:EXT_PHY. See Section 4.2.2.

Media Independent Interface (MII)

Symbol

LQFP Pin

No(s)

Dir

Description

COL

28

I

Collision Detect: The COL signal is asserted high asynchronously by the external

PMD upon detection of a collision on the medium. It will remain asserted as long as

the collision condition persists.

CRS

29

I

Carrier Sense: This signal is asserted high asynchronously by the external PMD

upon detection of a non-idle medium.

MDC

5

O

Management Data Clock: Clock signal with a maximum rate of 2.5 MHz used to

transfer management data for the external PMD on the MDIO pin.

MDIO

4

I/O

Management Data I/O: Bidirectional signal used to transfer management

information for the external PMD. (See Section 3.12.4 for details on connections

when MII is used.)

RXCLK

6

I

Receive Clock: A continuous clock, sourced by an external PMD device, that is

recovered from the incoming data. During 100 Mb/s operation RXCLK is 25 MHz

and during 10 Mb/s this is 2.5 MHz.

RXD3/MA9,

RXD2/MA8,

RXD1/MA7,

RXD0/MA6

12,

11,

10,

7

I

O

Receive Data: Sourced from an external PMD, that contains data aligned on nibble

boundaries and are driven synchronous to RXCLK. RXD[3] is the most significant

bit and RXD[0] is the least significant bit.

BIOS ROM Address: During external BIOS ROM access, these signals become

part of the ROM address.

RXDV/MA11

15

I

O

Receive Data Valid: Indicates that the external PMD is presenting recovered and

decoded nibbles on the RXD signals, and that RXCLK is synchronous to the

recovered data in 100 Mb/s operation. This signal will encompass the frame,

starting with the Start-of-Frame delimiter (JK) and excluding any End-of-Frame

delimiter (TR).

BIOS ROM Address: During external BIOS ROM access, this signal becomes part

of the ROM address.

RXER/MA10

14

I

O

Receive Error: Asserted high synchronously by the external PMD whenever it

detects a media error and RXDV is asserted in 100 Mb/s operation.

BIOS ROM Address: During external BIOS ROM access, this signal becomes part

of the ROM address.

RXOE

13

O

Receive Output Enable: Used to disable an external PMD while the BIOS ROM is

being accessed.

TXCLK

31

I

Transmit Clock: A continuous clock that is sourced by the external PMD. During

100 Mb/s operation this is 25 MHz +/- 100 ppm. During 10 Mb/s operation this clock

is 2.5 MHz +/- 100 ppm.

TXD3/MA15,

TXD2/MA14,

TXD1/MA13,

TXD0/MA12

25,

24,

23,

22

O

Transmit Data: Signals which are driven synchronous to the TXCLK for

transmission to the external PMD. TXD[3] is the most significant bit and TXD[0] is

the least significant bit.

BIOS ROM Address: During external BIOS ROM access, these signals become

part of the ROM address.

TXEN

30

O

Transmit Enable: This signal is synchronous to TXCLK and provides precise

framing for data carried on TXD[3-0] for the external PMD. It is asserted when

TXD[3-0] contains valid data to be transmitted.

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