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DP83816AVNG Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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DP83816AVNG Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 105 page 6 www.national.com 2.0 Pin Description (Continued) SERRN 98 I/O System Error: This signal is asserted low by DP83816 during address parity errors and system errors if enabled. STOPN 96 I/O Stop: This signal is asserted low by the target device to request the master device to stop the current transaction. TRDYN 93 I/O Target Ready: As a master, this signal indicates that the target is ready for the data during write operation and with the data during read operation. As a target, this signal will be asserted low when the (target) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYN signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN are asserted low. PMEN/ CLKRUNN 59 I/O Power Management Event/Clock Run Function: This pin is a dual function pin. The function of this pin is determined by the CLKRUN_EN bit 0 of the CLKRUN Control and Status register (CCSR). Default operation of this pin is PMEN. Power Management Event: This signal is asserted low by the DP83816 to indicate that a power management event has occurred. For pin connection please refer to Section 6.7. Clock Run Function: In this mode, this pin is used to indicate when the PCICLK will be stopped. 3VAUX 122 I PCI Auxiliary Voltage Sense: This pin is used to sense the presence of a 3.3V auxiliary supply in order to define the PME Support available. For pin connection please refer to Section 6.7. This pin has an internal weak pull down. PWRGOOD 123 I PCI bus power good: Connected to PCI bus 3.3V power, this pin is used to sense the presence of PCI bus power during the D3 power management state. This pin has an internal weak pull down. PCI Bus Interface Symbol LQFP Pin No(s) Dir Description |
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