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IC42S81600-6TG Datasheet(PDF) 9 Page - Integrated Circuit Solution Inc |
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IC42S81600-6TG Datasheet(HTML) 9 Page - Integrated Circuit Solution Inc |
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9 / 69 page  IC42S81600/IC42S81600L IC42S16800/IC42S16800L Integrated Circuit Solution Inc. 9 DR023-0E 6/11/2004 AC ELECTRICAL CHARACTERISTICS (At VDD = VDDQ = 3.3 ± 0.3V, VSS = VSSQ = 0V , unless otherwise noted) -6 -7 -8 Symbol Parameter Min. Max. Min. Max. Min. Max. Units tCK3 CLK Cycle Time CL= 3 6 — 7.5 — 8 — ns tCK2 CL= 2 7.5 — 10 — 10 — ns tAC3 CLK to valid output delay(1) CL= 3 — 5.4 — 5.4 — 6 ns tAC2 CL= 2 — 5.4 — 6 — 6 ns tCH CLK high pulse width 2.5 — 2.5 — 3 — ns tCL CLK low pulse width 2.5 — 2.5 — 3 — ns tCKE CKE setup time 1.5 — 1.5 — 2 — ns tCKH CKE hold time 0.8 — 0.8 — 1 — ns tAS Address setup time 1.5 — 1.5 — 2 — ns tAH Address hold time 0.8 — 0.8 — 1 — ns tCMS Command setup time 1.5 — 1.5 — 2 — ns tCMH Command hold time 0.8 — 0.8 — 1 — ns tDS Data input setup time 1.5 — 1.5 — 2 — ns tDH Data input hold time 0.8 — 0.8 — 1 — ns tOH3 Output data hold time(1) CL= 3 2.7 — 2.7 — 3 — ns tOH2 CL= 2 2.7 — 3 — 3 — ns tLZ CLK to output in low - Z 0— 0 — 0 — ns tHZ CLK to output in H - Z 2.7 5.4 2.7 5.4 3 6 ns tRC ROW cycle time 60.0 — 67.5 — 70 — ns tRAS ROW active time 42 100K 45 100K 50 100K ns tRCD RAS to CAS delay 18 — 20 — 20 — ns tRP Row precharge time 15 — 20 — 20 — ns tRRD Row active to active delay 12 — 15 — 20 — ns tT Transition time 110 1 10 1 10 ns tRSC Mode reg. set cycle 12 — 15 — 20 — ns tPDE Power down exit setup time 6 — 7.5 — 10 — ns tSRX Self refresh exit time 6 — 7.5 — 10 — ns tDPL Data in to Precharge 12 — 15 — 16 — ns tDAL Data in to Active/Refresh Delay Time 27 — 35 — 36 — ns tREF Refresh Time — 64 — 64 — 64 ms Notes: 1. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter. |
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