CY62146DV30L-55ZSXI datasheet(7/11 Pages) CYPRESS

Part #	CY62146DV30L-55ZSXI

Description	4-Mbit (256K x 16) Static RAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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7 / 11 page

CY62146DV30

Document #: 38-05339 Rev. *A

Page 7 of 11

Write Cycle No. 1 (WE Controlled)[15, 19, 20]

Write Cycle No. 2 (CE Controlled)[15, 19, 20]

Notes:

19. Data I/O is high impedance if OE = VIH.

20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.

21. During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

CE

WE

OE

tHZOE

DATAIN

NOTE 21

BHE/BLE

tBW

tSCE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

CE

ADDRESS

WE

DATA I/O

OE

NOTE 21

BHE/BLE

tBW

tSA

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