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ISPLSI2064V-100LT100I Datasheet(PDF) 5 Page - Lattice Semiconductor |
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ISPLSI2064V-100LT100I Datasheet(HTML) 5 Page - Lattice Semiconductor |
5 / 14 page 5 Specifications ispLSI 2064V External Timing Parameters Over Recommended Operating Conditions tpd1 UNITS -80 MIN. TEST COND. 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030/2064V 1 4 3 1 tsu2 + tco1 ( ) -60 MIN. MAX. MAX. DESCRIPTION # 2 PARAMETER A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 15.0 ns tpd2 A 2 Data Propagation Delay –– ns fmax A 3 Clock Frequency with Internal Feedback 80.0 – 61.7 – MHz fmax (Ext.) – 4 Clock Frequency with External Feedback –– MHz fmax (Tog.) – 5 Clock Frequency, Max. Toggle –– MHz tsu1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass –– ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass –– ns th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns tsu2 – 9 GLB Reg. Setup Time before Clock 9.0 – ns tco2 – 10 GLB Reg. Clock to Output Delay –– ns th2 – 11 GLB Reg. Hold Time after Clock 0.0 – ns tr1 A 12 Ext. Reset Pin to Output Delay –– ns trw1 – 13 Ext. Reset Pulse Duration 7.0 – ns tptoeen B 14 Input to Output Enable –– ns tptoedis C 15 Input to Output Disable –– ns tgoeen B 16 Global OE Output Enable –– ns tgoedis C 17 Global OE Output Disable –– ns twh – 18 External Synchronous Clock Pulse Duration, High 5.0 –– ns twl – 19 External Synchronous Clock Pulse Duration, Low 5.0 –– ns 64.5 100 7.0 6.5 – – 7.5 – 14.0 – 15.0 15.0 10.0 10.0 15.0 51.3 71.4 9.0 0.0 11.0 0.0 8.0 7.0 7.0 20.0 8.5 9.5 16.0 18.0 18.0 12.0 12.0 -100 MIN. MAX. – 7.5 – 102 – – – – – 0.0 7.0 – 0.0 – 5.0 – – – – 4.0 – 4.0 – 83.3 125 5.5 5.0 – – 6.3 – 12.0 – 13.0 13.0 7.5 7.5 12.0 |
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