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MSM54V12222A Datasheet(PDF) 5 Page - OKI electronic componets

Part No. MSM54V12222A
Description  262,214 Words x 12 Bits FIELD MEMORY
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Maker  OKI [OKI electronic componets]
Homepage  http://www.oki.com
Logo OKI - OKI electronic componets

MSM54V12222A Datasheet(HTML) 5 Page - OKI electronic componets

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MSM54V12222A
OKI Semiconductor
5
OPERATION
Write Operation
The write operation is controlled by tree clocks, SWCK, RSTW, and WE. Write operation is accomplished
by cycling SWCK and holding WE high after write address pointer reset operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e. SWCK
cycles while WE is high. To transfer the last data, which at that time are stored in the serial data registers
attached to DRAM array, to the DRAM array, an RSTW operation is required after the last SWCK cycle.
Note that every write timing of MSM54V12222A is delayed by one clock compared wih read timings for
easy cascading without any interface delay devices.
Write Reset : RSTW
The first positive transition of SWCK after RSTW going high resets the write address counters to zero.
RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function
is solely controlled by SWCK rising edge after high level of RSTW, the states of WE and IE are don't care
in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must have been low for at least
two SWCK cycles.
Data Inputs : Din0-11
Write Clock : SWCK
The SWCK latches the input data on chip when WE is high and also increments the internal write address
pointer. Data-in setup time, tDS and hold time, tDH, are referenced to the rising edge of SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level
disables the input and holds the internal write address pointer. There are no WE disable time (low) and
WE enable time (high) restrictions because MSM54V12222A is fully static operation as long as power is
on. Note that WE setup and hold times are referenced to the rising edge of SWCK.
Input Enable : IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address
pointer is always incremented by cycling SWCK regardless of IE level. Note that IE setup and hold times
are referenced to the rising edge of SWCK.


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