IDT77V1254L25 datasheet(1/47 Pages) IDT

Part #	IDT77V1254L25

Description	Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks

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Manufacturer	IDT [Integrated Device Technology]

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September 21, 2001

 2001 Integrated Device Technology, Inc.

DSC 6003

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

Quad Port PHY (Physical Layer)

for 25.6 and 51.2

ATM Networks

Features List

Performs the PHY-Transmission Convergence (TC) and

Physical Media Dependent (PMD) Sublayer functions for

four 25.6 Mbps ATM channels

Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5

specifications for 25.6 Mbps physical interface

Also operates at 51.2 Mbps data rate

UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface

3-Cell Transmit & Receive FIFOs

LED Interface for status signalling

Supports UTP Category 3 and 5 physical media

Interfaces to standard magnetics

Low-Power CMOS

3.3V supply with 5V tolerant inputs

144-pin PQFP Package (28 x 28 mm)

Commercial and Industrial Temperature Ranges

Description

The IDT77V1254L25 is a member of IDT's family of products

supporting Asynchronous Transfer Mode (ATM) data communications

and networking. The IDT77V1254L25 implements the physical layer for

25.6 Mbps ATM, connecting four serial copper links (UTP Category 3

and 5) to one ATM layer device such as a SAR or a switch ASIC. The

IDT77V1254L25 also operates at 51.2 Mbps, and is well suited to back-

plane driving applications.

The 77V1254L25-to-ATM layer interface is selectable as one of three

options: 16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or

quadruple 4-bit DPI (Data Path Interface).

The IDT77V1254L25 is fabricated using IDT's state-of-the-art CMOS

technology, providing the highest levels of integration, performance and

reliability, with the low-power consumption characteristics of CMOS.

Block Diagram

RX C L K

Clock R eco ve ry

5B /4B

E n coding/

De cod ing

P/S an d S /P

NRZ I

Scra m bler/

De scra m b ler

TX /R X A TM

CellF IF O

TX 0

RX 0

Clock R eco ve ry

5B /4B

E n coding/

De cod ing

P/S an d S /P

NRZ I

Scra m bler/

De scra m b ler

TX /R X A TM

CellF IF O

Tx 1

Rx 1

Clock R eco ve ry

5B /4B

E n coding/

De cod ing

P/S an d S /P

NRZ I

Scra m bler/

De scra m b ler

TX /R X A TM

CellF IF O

TX 2

RX 2

Clock R eco ve ry

5B /4B

E n coding/

De cod ing

P/S an d S /P

NRZ I

Scra m bler/

De scra m b ler

TX /R X A TM

CellF IF O

TX 3

RX 3

PH Y -A T M

Interface

(U T O P IAor D P I)

Microprocesso r

Interface

T X D A T A [15:0]

TX C L K

TXEN

RX D A T A [15:0 ]

RXEN

4

R X LE D [3:0 ]

T X LE D [3:0]

RXREF

TXREF

T X A D D R [4 :0 ]

R XAD D R [4 :0]

+

-

+

-

+

-

+

-

+

-

+

-

T XSO C

TX C L A V

T X PAR IT Y

MO D E [1:0 ]

RX S O C

RX CL A V

RX P A R IT Y

3 505 d rw 0 1

+

-

+

-

INT

RST

RD

WR

AL E

AD [7:0]

CS

OS C

Driver

.

IDT77V1254L25

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