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IDT77V1254L25 Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT77V1254L25 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 47 page 2 of 47 September 21, 2001 IDT77V1254L25 Applications Up to 204.8Mbps backplane transmission Rack-to-rack short links ATM Switches 77V1254L25 Overview The 77V1254L25 is a four port implementation of the physical layer standard for 25.6Mbps ATM network communications as defined by ATM Forum document af-phy-040.000 and ITU-T I.432.5. The physical layer is divided into a Physical Media Dependent sub layer (PMD) and Transmission Convergence (TC) sub layer. The PMD sub layer includes the functions for the transmitter, receiver and clock recovery for opera- tion across 100 meters of category 3 and 5 unshielded twisted pair (UTP) cable. This is referred to as the Line Side Interface. The TC sub layer defines the line coding, scrambling, data framing and synchroniza- tion. On the other side, the 77V1254L25 interfaces to an ATM layer device (such as a switch core or SAR). This cell level interface is configurable as either 8-bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2, or as four 4-bit DPI interfaces, as determined by two MODE pins. This is referred to as the PHY-ATM Interface. The pinout and front page block diagram are based on the Utopia 2 configuration. Table 2 shows the corre- sponding pin functions for the other two modes, and Figure 2 and Figure 3 show functional block diagrams. The 77V1254L25 is based on the 77105, and maintains significant register compatibility with it. The 77V1254L25, however, has additional register features, and also duplicates most of its registers to provide significant independence between the four ports. Access to these status and control registers is through the utility bus. This is an 8-bit muxed address and data bus, controlled by a conven- tional asynchronous read/write handshake. Additional pins permit insertion and extraction of an 8kHz timing marker, and provide LED indication of receive and transmit status. Auto-Synchronization and Good Signal Indication The 77V1254L25 features a new receiver synchronization algorithm that allow it to achieve 4b/5b symbol framing on any valid data stream. This is an improvement on earlier products which could frame only on the escape symbol, which occurs only in start-of-cell or 8kHz (X8) timing marker symbol pairs. ATM25 transceivers always transmit valid 4b/5b symbols, allowing the 77V1254L25 receive section to achieve symbol framing and properly indicate receive signal status, even in the absence of ATM cells or 8kHz (X8) timing markers in the receive data stream. A state maching moni- tors the received symbols and asserts the “Good Signal” status bit when a valid signal is being received. “Good Signal” is deasserted and the receive FIFO is disabled when the signal is lost. This is sometimes referred to as Loss of Signal (LOS). Operation AT 51.2 Mbps In addition to operation at the standard rate of 25.6 Mbps, the 77V1254L25 is also specified to operate at 51.2 Mbps. Except for the doubled bit rate, all other aspects of operation are identical to the 25.6 Mbps mode. The rate is determined by the frequency of the clock applied to the OSC input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2 Mbps line rate. All ports operate at the same frequency. See Figure 36 for recommended line magnetics. Magnetics for 51.2 Mbps operation have a higher bandwidth than magnetics optimized for 25.6 Mbps. Functional Description Transmission Convergence (TC) Sub Layer Introduction The TC sub layer defines the line coding, scrambling, data framing and synchronization. Under control of a switch interface or Segmenta- tion and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53- byte ATM cell, scrambles the data, appends a command byte to the beginning of the cell, and encodes the entire 53 bytes before transmis- sion. These data transformations ensure that the signal is evenly distrib- uted across the frequency spectrum. In addition, the serialized bit stream is NRZI coded. An 8kHz timing sync pulse may be used for isochronous communications. Data Structure and Framing Each 53-byte ATM cell is preceded with a command byte. This byte is distinguished by an escape symbol followed by one of 17 encoded symbols. Together, this byte forms one of seventeen possible command bytes. Three command bytes are defined: 1. X_X (read: 'escape' symbol followed by another 'escape'): Start- of-cell with scrambler/descrambler reset. 2. X_4 ('escape' followed by '4'): Start-of-cell without scrambler/ descrambler reset. 3. X_8 ('escape' followed by '8'): 8kHz timing marker. This command byte is generated when the 8kHz sync pulse is detected, and has priority over all line activity (data or command bytes). It is transmitted immediately when the sync pulse is detected. When this occurs during a cell transmission, the data transfer is temporarily interrupted on an octet boundary, and the X_8 command byte is inserted. This condition is the only allowed interrupt in an otherwise contiguous transfer. Below is an illustration of the cell structure and command byte usage: {X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell} ... In the above example, the first ATM cell is preceded by the X_X start-of-cell command byte which resets both the transmitter-scrambler and receiver-descrambler pseudo-random nibble generators (PRNG) to their initial states. The following cell illustrates the insertion of a start-of- cell command without scrambler/descrambler reset. During this cell's transmission, an 8kHz timing sync pulse triggers insertion of the X_8 8kHz timing marker command byte. |
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