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6N137 Datasheet(PDF) 4 Page - Fairchild Semiconductor

Part No. 6N137
Description  HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

6N137 Datasheet(HTML) 4 Page - Fairchild Semiconductor

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Single-channel: 6N137, HCPL-2601, HCPL-2611 Dual-Channel: HCPL-2630, HCPL-2631 Rev. 1.0.3
Transfer Characteristics (TA = -40 to +85°C Unless otherwise specified)
Isolation Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
** All Typicals at VCC = 5V, TA = 25°C
NOTES
1.
The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and
GND pins of each device.
2.
Each channel.
3.
Enable Input - No pull up resistor required as the device has an internal pull up resistor.
4.
tPLH -Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V
level on the LOW to HIGH transition of the output voltage pulse.
5.
tPHL -Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V
level on the HIGH to LOW transition of the output voltage pulse.
6.
tr -Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7.
tf -Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8.
tELH -Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse to
the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
9.
tEHL -Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse to
the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH -The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT
> 2.0 V). Measured in volts per microsecond (V/µs).
11. CML -The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state (i.e.,
VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
DC Characteristics
Test Conditions Symbol
Min
Typ**
Max
Unit
High Level Output Current
(VCC = 5.5 V, VO = 5.5 V)
(IF = 250 µA, VE = 2.0 V) (Note 2)
IOH
100
µA
Low Level Output Current
(VCC = 5.5 V, IF = 5 mA)
(VE = 2.0 V, ICL = 13 mA) (Note 2)
VOL
.35
0.6
V
Input Threshold Current
(VCC = 5.5 V, VO = 0.6 V,
VE = 2.0 V, IOL = 13 mA)
IFT
3
5
mA
Characteristics
Test Conditions Symbol
Min
Typ**
Max
Unit
Input-Output
Insulation Leakage
Current
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 12)
II-O
1.0*
µA
Withstand Insulation Test Voltage
(RH < 50%, TA = 25°C)
(Note 12) ( t = 1 min.)
VISO
2500
VRMS
Resistance (Input to Output)
(VI-O = 500 V) (Note 12)
RI-O
1012
Capacitance (Input to Output)
(f = 1 MHz) (Note 12)
CI-O
0.6
pF


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