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ISPPAC81-01SI Datasheet(PDF) 4 Page - Lattice Semiconductor |
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ISPPAC81-01SI Datasheet(HTML) 4 Page - Lattice Semiconductor |
4 / 20 page Lattice Semiconductor ispPAC81 Data Sheet 4 Pin Descriptions Connection Notes 1. All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be selected externally by reversing pin connections. 2. All analog output pins are “hard-wired” to internal output devices and should be left open if not used. VOUT+ and VOUT- should not be tied together as unnecessary power will be dissipated. 3. When the signal input is single-ended, the other half of the unused differential input must be connected to a DC common-mode reference (usually VREFOUT, 2.5V). Absolute Maximum Ratings Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7V Logic and Analog Input Voltage Applied. . . . . . . . . . . . . . . 0 to VS Logic and Analog Output Short Circuit Duration . . . . . . Indefinite Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . . .260°C Ambient Temperature with Power Applied . . . . . . . . -55 to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied. Pin(s) Symbol Name Description 1 TMS Test Mode Select Serial interface logic mode select pin (input). JTAG interface mode only. 2 TCK Test Clock Serial interface logic clock pin (input). JTAG and SPI interface modes. 3 TDI Test Data In Serial interface logic pin (input) for both JTAG and SPI opera- tion modes. 4 TDO Test Data Out Serial interface logic pin (output) for both JTAG and SPI opera- tion modes. Input data valid on falling edge of TCK (JTAG), or on rising edge of CS (SPI). 5 CS Chip Select Chip select logic input pin. SPI data latch. 6 CAL Auto-Calibrate Digital pin (input). Commands an auto-calibration sequence on a rising edge. 7 ENSPI Enable SPI Mode Enable SPI logic input pin. When high, causes serial port to run in SPI mode. 8 GND Ground Ground pin. Should normally be connected to the analog ground plane. 9 VREFOUT Common-Mode Reference Common-mode voltage reference output pin (+2.5V nominal). Must be bypassed to GND with a 1µF capacitor. 10, 11 IN Inputs (+ or -) Differential input pins, using two pins (e.g., IN+ and IN-). Plus or minus components of VIN, where differential VIN = VIN+ - VIN-. 12, 15 TEST Test Pin Test pin. Connect to GND for proper circuit operation. 13, 14 OUT Outputs (+ or -) Differential output pins, using two pins (e.g., OUT+ and OUT-). Complementary with respect to VREFOUT. Differential VOUT = VOUT+ - VOUT-. 16 VS Supply Voltage Analog supply voltage pin (5V nominal). Should be bypassed to GND with 1µF and .01µF capacitors. |
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