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XRT75L00D Datasheet(PDF) 41 Page - Exar Corporation |
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XRT75L00D Datasheet(HTML) 41 Page - Exar Corporation |
41 / 92 page XRT75L00D REV. 1.0.2 E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 36 7.0 SERIAL HOST INTERFACE: A flexible serial microprocessor interface is incorporated in the XRT75L00D. The interface is generic and is designed to support the common microprocessors/microcontrollers. The XRT75L00D operates in Host mode when the HOST/HW pin is tied “High”. The serial interface includes a serial clock (SClk), serial data input (SDI), serial data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown in Figure 11. The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the processor. When the XRT75L00D is configured in Host mode, the following input pins,TxLEV, TAOS, RLB, LLB, E3, STS- 1/DS3, REQEN, JATx/Rx, JA0 and JA1 are disabled and must be connected to ground. Table 14 below illustrates the functions of the shared pins in either Host mode or in Hardware mode. NOTE: While configured in Host mode, the TxON input pin will be active if the TxON bit in the control register is set to “1”, and can be used to turn on and off the transmit output drivers. This permits a system designed for redundancy to quickly switch out a defective line card and switch-in the backup line card. TABLE 14: FUNCTIONS OF SHARED PINS PIN NUMBER IN HOST MODE IN HARDWARE MODE 24 CS RxClkINV 26 SClk TxClkINV 25 SDI RxON 27 SDO RxMON 28 INT LOSMUT TABLE 15: REGISTER MAP AND BIT NAMES ADDRESS (HEX) PARAMETER NAME DATA BITS 76 5 43210 0x00 APS/Redundancy (read/write) Reserved Reserved Reserved RxON Reserved Reserved Reserved TxON 0x01 Interrupt Enable (read/write) Reserved CNT_SATIE PRBSIE FLIE RLOLIE RLOSIE DMOIE 0x02 Interrupt Status (reset on read) Reserved CNT_SATIS PRBSIS FLIS RLOLIS RLOSIS DMOIS 0x03 Alarm Status (read only) Reserved PRBSLS DLOS ALOS FL RLOL RLOS DMO 0x04 Transmit Control (read/write) Reserved TxMON INSPRBS Reserved TAOS TxClkINV TxLEV 0x05 Receive Control (read/write) Reserved DLOSDIS ALOSDIS RxClkINV LOSMUT RxMON REQEN 0x06 Block Control (read/write) Reserved PRBSEN RLB LLB E3 STS1/ DS3 SR/DR 0x07 Jitter Attenuator (read/write) Reserved DFLCK PNTRST JA1 JATx/Rx JA0 |
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