Product Brief

ICS1893AF

Page 3

Document Revision: 5 April 2002

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Pins LSTA (link status) and LOCK (rec. PLL locked) are not brought out.

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LSTA and LOCK provided redundant information already available with the P2LI pin. P2LI

indicates the Link is valid.

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Input pin TXER is removed and tied low inside the package. The TXER function is still available by using

the Extended Control Register Reg 16 Bit 2. Most applications tied the TXER pin to VSS.

ICS1893AF Shared Features

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The same silicon die is used in the ICS1893AF and ICS1893Y-10.

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Only the package type is different.

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The ICS1893AF offers the same .35µ 3.3V low power operation.

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Parametric specifications and timing diagrams same as ICS1893Y-10.

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See ICS1893 Data Sheet for specification and timing details.

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Both the ICS1893Y-10 and the ICS1893AF incorporate Digital Signal Processing in their PMD Sub layer,

thereby allowing them to transmit and receive data with Unshielded Twisted Pair (UTP) Category 5

cables up to 150 meters in length. In addition, this ICS-patented, technology has allowed the ICS1893Y-

10 and ICS1893AF to address the effects of Baseline Wander correction with UTP cable lengths up to

150m.

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Both ICS1893AF and ICS1893Y-10 have improved 10Base-T Squelch operation.

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The 1893AF uses the same twisted pair transmitter and receive circuits and therefore the same

recommended board layout techniques apply. See Typical Board Layout section.

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Both share improved transmit circuits resulting in decrease in the magnitude of the 10Base-T harmonic

content generated during transmission (reference ISO/IEC 8802-3: 1993 Clause 8.3.1.3).

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Both use digital PLL technology resulting in lower jitter and improved stability.

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Both seed the transmit stream cipher with the PHY address. This minimizes cross-talk, EMI and noise in

multiple Phy applications.

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The MDIO Maintenance interface with the MDIO and MDC pins along with all internal registers are

preserved in the ICS1893AF. This allows software configuring for FD/HD, 10baseT, 100baseTX and

Auto-Negotiation to be configurable by the MDIO maintenance interface. Default setting is Auto-

Negotiation Enable. All register settings are the same as in the ICS1893 datasheet.

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The ICS1893AF preserves the dual purpose LED/Phy Address control pins as in the ICS1893Y-10. The

captured address seeds the scrambler for lower EMI in for multiple Phy applications.

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All Auto-Negotiation features are preserved in the ICS1893AF. The reset default mode is A_N enabled.

The A_N parallel detect feature is preserved for legacy interoperability.

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Both support the Auto-Negotiation Next Page functions as described in IEEE Std 802.3u-1995 clause

28.2.3.4

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Both support Management Frame (MF) Preamble Suppression.

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Both support backward compatibility with the ICS1890 Management Registers