K6R3024V1D

CMOS SRAM

Revision 1.0

- 5 -

December 2001

for AT&T

READ CYCLE*

Parameter

Symbol

K6R3024V1D-09

K6R3024V1D-10

K6R3024V1D-12

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

9

-

10

-

12

-

ns

Address Access Time

-

9

-

10

-

12

ns

Chip Select to Output

-

9

-

10

-

12

ns

Output Enable to Valid Output

-

4

-

5

-

6

ns

Chip Enable to Low-Z Output

3

-

3

-

3

-

ns

Output Enable to Low-Z Output

0

-

0

-

0

-

ns

Chip Disable to High-Z Output

0

4

0

5

0

6

ns

Output Disable to High-Z Output

0

5

0

6

0

7

ns

Output Hold from Address Change

3

-

3

-

3

-

ns

Chip Select to Power-Up Time

0

-

0

-

0

-

ns

Chip Deselect to Power DownTime

-

9

-

10

-

12

ns

WRITE CYCLE*

* This parameter is guaranteed by design but not tested.

These specifications are for the individual K6R3024V1D Static RAMs.

Parameter

Symbol

K6R3024V1D-09

K6R3024V1D-10

K6R3024V1D-12

Unit

Min

Max

Min

Max

Min

Max

Write Cycle Time

9

-

10

-

12

-

ns

Chip Select to End of Write

7

-

7

-

8

-

ns

Address Set-up Time

0

-

0

-

0

-

ns

Address Valid to End of Write

7

-

7

-

8

-

ns

Write Pulse Width(OE High)

7

-

7

-

8

-

ns

Write Pulse Width(OE Low)

9

-

9

-

10

-

ns

Write Recovery Time

0

-

0

-

0

-

ns

Write to Output High-Z

0

5

0

5

0

5

ns

Data to Write Time Overlap

5

-

5

-

7

-

ns

Data Hold from Write Time

0

-

0

-

0

-

ns

End Write to Output Low-Z

3

-

3

-

3

-

ns