K6R3024V1D

CMOS SRAM

Revision 1.0

- 6 -

December 2001

for AT&T

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

device.

5. Transition is measured

±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

CS

Address

OE

Data out

Valid Data

50%

50%

Current

Address

Data Out

Previous Valid Data

Valid Data

TIMMING DIAGRAMS