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ICS950401 Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS950401 Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 14 page 2 ICS950401 0499C—11/01/04 Pin Descriptions PIN PIN PIN # NAME TYPE 1 *FS0/REF0 I/O Frequency select latch input pin / 14.318 MHz reference clock. 2 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 3 X1 IN Crystal input, Nominally 14.318MHz. 4 X2 OUT Crystal output, Nominally 14.318MHz 5 GND PWR Ground pin. 6 *PCI33/HT66SEL# IN Input for PCI33/HT66 select. 0= 66.66MHz, 1= 33.33MHz, 7 PCICLK33/HT66_0 IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input. 8 PCICLK33/HT66_1 IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input. 9 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 10 GND PWR Ground pin. 11 PCICLK33/HT66_2 IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input. 12 NC NC No Connect 13 PCICLK0 OUT PCI clock output. 14 PCICLK1 OUT PCI clock output. 15 GND PWR Ground pin. 16 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 17 PCICLK2 OUT PCI clock output. 18 PCICLK3 OUT PCI clock output. 19 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 20 GND PWR Ground pin. 21 PCICLK4 OUT PCI clock output. 22 PCICLK5 OUT PCI clock output. 23 PCICLK_F I/O Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin. 24 *PCI_STOP# I/O Input select pin, Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. 25 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 26 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 27 GND PWR Ground pin. 28 24_48MHz/Sel24_48#* I/O 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. 29 VDD PWR Power supply, nominal 3.3V 30 GND PWR Ground pin. 31 48MHz OUT 48MHz clock output. 32 VDDA PWR 3.3V power for the PLL core. 33 GNDA PWR Ground pin for the PLL core. 34 GND PWR Ground pin. 35 VDD PWR Power supply, nominal 3.3V 36 CPUCLKC1 OUT Complementory clock of differential CPU outputs. Push-pull requires external termination. 37 CPUCLKT1 OUT True clock of differential CPU outputs. Push-pull requires external termination. 38 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 39 GND PWR Ground pin. 40 CPUCLKC0 OUT Complementory clock of differential CPU outputs. Push-pull requires external termination. 41 CPUCLKT0 OUT True clock of differential CPU outputs. Push-pull requires external termination. 42 GNDA PWR Ground pin for the PLL core. 43 VDDA PWR 3.3V power for the PLL core. 44 SPREAD* IN Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable spread spectrum functionality. 45 REF2/FS2* I/O 14.318 MHz reference clock / Frequency select latch input pin. 46 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 47 GND PWR Ground pin. 48 REF1/FS1* I/O 14.318 MHz reference clock / Frequency select latch input pin. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength DESCRIPTION |
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