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CC3135 Datasheet(PDF) 63 Page - Texas Instruments |
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CC3135 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 78 page 
63 CC3135 www.ti.com SWAS037 – JANUARY 2019 Submit Documentation Feedback Product Folder Links: CC3135 Applications, Implementation, and Layout Copyright © 2019, Texas Instruments Incorporated 7.2 PCB Layout Guidelines This section details the PCB guidelines to speed up the PCB design using the CC3135 VQFN device. Follow these guidelines ensures that the design will minimize the risk with regulatory certifications including FCC, ETSI, and CE. For more information, see CC3135 and CC3235 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines. 7.2.1 General PCB Guidelines Use the following PCB guidelines: • Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended layers for signals and ground. • Ensure that the VQFN PCB footprint follows the information in Section 9. • Ensure that the VQFN PCB GND and solder paste follow the recommendations provided in CC3135 and CC3235 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines. • Decoupling capacitors must be as close as possible to the VQFN device. 7.2.2 Power Layout and Routing Three critical DC/DC converters must be considered for the CC3135 device. • Analog DC/DC converter • PA DC/DC converter • Digital DC/DC converter Each converter requires an external inductor and capacitor that must be laid out with care. DC current loops are formed when laying out the power components. 7.2.2.1 Design Considerations The following design guidelines must be followed when laying out the CC3135 device: • Ground returns of the input decoupling capacitors (C12, C14, and C21) should be routed on Layer 2 using thick traces to isolate the RF ground from the noisy supply ground. This step is also required to meet the IEEE spectral mask specifications. • Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44). • Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24). • Place all decoupling capacitors as close to the respective pins as possible. • Power budget—the CC3135 device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, for 24 ms during the calibration cycle. • Ensure the power supply is designed to source this current without any issues. The complete calibration (TX and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms. • The CC3135 device contains many high-current input pins. Ensure the trace feeding these pins can handle the following currents: – VIN_DCDC_PA input (pin 39) maximum 1 A – VIN_DCDC_ANA input (pin 37) maximum 600 mA – VIN_DCDC_DIG input (pin 44) maximum 500 mA – DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum 1 A – DCDC_PA_OUT output node (pin 42) maximum 1 A – DCDC_ANA_SW switching node (pin 38) maximum 600 mA – DCDC_DIG_SW switching node (pin 43) maximum 500 mA – VDD_PA_IN supply (pin 33) maximum 500 mA |
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