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AK4631 Datasheet(PDF) 22 Page - Asahi Kasei Microsystems |
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AK4631 Datasheet(HTML) 22 Page - Asahi Kasei Microsystems |
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22 / 69 page  ASAHI KASEI [AK4631] MS0317-J-01 2004/11 - 22 - 機能説明 システムクロック 外部との I/Fモードは以下の4通りの方法があります。（See Table 1 and Table 2） Mode PMPLL bit M/S bit PLL3-0 bit MCKPD bit Figure PLL Master Mode 1 1 See Table 4 0 Figure 18 PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) 1 0 See Table 4 0 Figure 19 PLL Slave Mode 2 (PLL Reference Clock: FCK or BICK pin) 1 0 See Table 4 1 Figure 20 EXT Slave Mode 0 0 X 0 Figure 21 Don’t Care (Note 29) 0 1 X X - Table 1. Clock Mode Setting (X: Don’t care) Note 29. クロックモード設定の都合上、このモードを通過する区間では、MCKO, FCK, BICK から正常でない周波数 のクロックが出力されます。 Mode MCKO bit MCKO pin MCKI pin BICK pin FCK pin 0 “L” Output PLL Master Mode 1 256fs Output Master Clock Input for PLL (Note 30) 16fs/32fs/64fs Output 1fs Output 0 “L” Output PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) 1 256fs Output Master Clock Input for PLL (Note 30) 16fs/32fs/64fs Input 1fs Input PLL Slave Mode 2 (PLL Reference Clock: FCK or BICK pin) 0 “L” Output GND 16fs/32fs/64fs Input 1fs Input EXT Slave Mode 0 “L” Output 256fs/ 512fs/ 1024fs Input ≥ 32fs Input 1fs Input Note 30. 11.2896MHz/12MHz/12.288MHz/13.5MHz/24MHz/27MHz Table 2. Clock pins state in Clock Mode [MCKIのプルダウン抵抗について] マスタクロックを入力する時は、 MCKPD bit = “0”にして下さい。入力がフローティングになるときはMCKPD bit = “1” (Default) にして、25kΩ (typ) で内部プルダウンします。 MCKI AK4631 25k Ω MCKPD bit ="0" Figure 17. Pull-down resistor of MCKI pin |
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