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ADC12DJ3200 Datasheet(PDF) 76 Page - Texas Instruments |
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ADC12DJ3200 Datasheet(HTML) 76 Page - Texas Instruments |
76 / 155 page 76 ADC12DJ3200 SLVSD97 – JUNE 2017 www.ti.com Product Folder Links: ADC12DJ3200 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated input that is being sampled (INA+/– or INB+/–), the bank that is being trimmed or the ADC core that is being trimmed. It is not expected that the user must change the trim values as operating conditions change, however optimal performance may be obtained by doing so. Any custom trimming must be done on a per device basis due to process variations, meaning that there is no global optimal setting for all parts. See Trimming for information about the available trim parameters and associated registers. 7.4.6.1 Foreground Calibration Mode Foreground calibration requires the ADC to stop converting the analog input signals during the procedure. Foreground calibration always runs on power up and the user must wait a sufficient time before programming the device to guarantee that the calibration is finished. Foreground calibration can be initiated by triggering the calibration engine. The trigger source can be either the CAL_TRIG pin or CAL_SOFT_TRIG (Calibration Software Trigger Register (address = 0x06C) [reset = 0x01]) and is chosen by setting CAL_TRIG_EN (Calibration Pin Configuration Register (address = 0x06B) [reset = 0x00]). 7.4.6.2 Background Calibration Mode Background calibration mode allows the ADC to continuously operate, with no interruption of data. This is accomplished by activating an extra ADC core which is calibrated and then takes over operation for one of the other previously active ADC cores. Once that ADC core is taken off-line it is then calibrated and can in turn take over to allow the next ADC to be calibrated. This process operates continuously, ensuring the ADC cores are always providing the optimum performance regardless of system operating condition changes. Due to the additional active ADC core, Background calibration mode has increased power consumption in comparison to Foreground calibration mode. The low-power background calibration (LPBG) mode discussed next provides reduced average power consumption in comparison with the standard background calibration mode. Background calibration can be enabled by setting CAL_BG (Calibration Configuration 0 Register (address = 0x062) [reset = 0x01]). CAL_TRIG_EN should be set to 0 and CAL_SOFT_TRIG should be set to 1. Great care has been taken to minimize effects on converted data as the core switching process occurs, however, small brief glitches may still be seen on the converter data as the cores are swapped. Please refer to the Typical Characteristic section of the datasheet for examples of the possible glitches in sine-wave and DC signals. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores. Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN=1 to enable the low- power background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps before waking up for calibration (if LP_EN=1 and LP_TRIG=0). LP_WAKE_DLY sets how long the core is allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is an increase in power consumption during the ADC core calibration. The power consumption will roughly alternate between the power consumption in foreground calibration when the spare ADC core is sleeping to the power consumption in background calibration when the spare ADC is being calibrated. The power supply network should be designed to be able to handle the transient power requirements for this mode. 7.4.7 Offset Calibration Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores, however the input buffers sits outside of the calibration loop and therefore their offsets are not calibrated by the standard calibration process. In both dual channel mode and single channel mode uncalibrated input buffer offsets result in a shift in the mid-code output (DC offset) with no input. Further, in single channel mode uncalibrated input buffer offsets can result in a fixed spur at FS/2. A separate calibration is provided to correct the input buffer offsets. |
Similar Part No. - ADC12DJ3200_19 |
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Similar Description - ADC12DJ3200_19 |
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