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ADC12DJ3200 Datasheet(PDF) 46 Page - Texas Instruments

Part # ADC12DJ3200
Description  6.4-GSPS Single Channel or 3.2-GSPS Dual Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ3200 Datasheet(HTML) 46 Page - Texas Instruments

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ADC12DJ3200
SLVSD97 – JUNE 2017
www.ti.com
Product Folder Links: ADC12DJ3200
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Copyright © 2017, Texas Instruments Incorporated
The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When
SYSREF_ZOOM is set to '0', the delay steps are more coarse. When SYSREF_ZOOM is set to '1', the delay
steps finer steps. See Switching Characteristics for delay step sizes when SYSREF_ZOOM is enabled and
disabled. In general, SYSREF_ZOOM should always be used (SYSREF_ZOOM = 1) unless a transition region
(defined by 1's in SYSREF_POS) is not seen, such as could be the case for low clock rates. Bits 0 and 23 of
SYSREF_POS will always be set to '1' since it cannot be determined if these settings are close to a timing
violation, although the actual valid window could extend beyond these sampling positions. The value
programmed into SYSREF_SEL is the decimal number representing the desired bit location in SYSREF_POS.
Table 6 shows some example SYSREF_POS readings and the optimal SYSREF_SEL settings. Although 24
sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows selection of the
first 16 sampling positions, corresponding to SYSREF_POS bits 0 to 15. The additional SYSREF_POS status
bits are intended only to provide additional knowledge of the SYSREF valid window. In general, lower values of
SYSREF_SEL should be selected due to variation of the delays over supply voltage, however in the fourth
example a value of 15 provides additional margin and may be selected instead.
Table 6. Examples of SYSREF_POS Readings and SYSREF_SEL Selections
SYSREF_POS[23:0]
OPTIMAL SYSREF_SEL
SETTING
0x02E[7:0]
(Largest Delay)
0x02D[7:0]
0x02C[7:0]
(Smallest Delay)
b10000000
b01100000
b00011001
8 or 9
b10011000
b00000000
b00110001
12
b10000000
b01100000
b00000001
6 or 7
b10000000
b00000011
b00000001
4 or 15
b10001100
b01100011
b00011001
6
7.3.4.3.2
Automatic SYSREF Calibration
ADC12DJ3200 has an automatic SYSREF calibration feature to alleviate the often challenging setup and hold
times associated with capturing SYSREF for giga-sample data converters. Automatic SYSREF Calibration uses
the tAD Adjust feature to shift the device clock to maximize the SYSREF setup and hold times or align the
sampling instance based on the SYSREF rising edge.
ADC12DJ3200 must have a proper device clock applied and be programmed for normal operation before starting
Automatic SYSREF Calibration. When ready to initiate Automatic SYSREF Calibration a continuous SYSREF
signal should be applied. Note that SYSREF must be a continuous (periodic) signal when using Automatic
SYSREF Calibration. Start the calibration process by setting SRC_EN high in Figure 173 after configuring
Automatic SYSREF Calibration using the SRC_CFG register. Upon setting SRC_EN high ADC12DJ3200
searches for the optimal tAD Adjust setting until the device clock falling edge is internally aligned to the SYSREF
rising edge. TAD_DONE in Figure 175 can be monitored to ensure that SYSREF calibration has finished. By
aligning the device clock falling edge with the SYSREF rising edge Automatic SYSREF Calibration maximizes
the internal SYSREF setup and hold times relative to the device clock while also setting the sampling instant
based on the SYSREF rising edge. After Automatic SYSREF Calibration finishes the rest of the startup
procedure can be performed to finish bringing up the system.
For multi-device synchronization the timing of the SYSREF rising edge should be matched at all devices and
therefore trace lengths should be matched from a common SYSREF source to each ADC12DJ3200. Any skew
between the SYSREF rising edge at each device will result in additional error in the sampling instance between
devices, however repeatable deterministic latency from system startup to startup through each device should still
be achieved. No other design requirements are needed in order to achieve multi-device synchronization as long
as a proper elastic buffer release point is chosen in the receiver.
A timing diagram of the SYSREF calibration procedure is shown in Figure 67. The optimized setup and hold
times are shown as tSU(OPT) and tH(OPT), respectively. Device clock and SYSREF are referred to as "internal" in
this diagram since the phase of the internal signals are aligned within the device and not to the external (applied)
phase of device clock or SYSREF.


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