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ADC12DJ3200 Datasheet(PDF) 27 Page - Texas Instruments

Part # ADC12DJ3200
Description  6.4-GSPS Single Channel or 3.2-GSPS Dual Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ3200 Datasheet(HTML) 27 Page - Texas Instruments

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Fin (MHz)
0
2000
4000
6000
8000
10000
-85
-80
-75
-70
-65
-60
-55
-50
D130
H2 (dBFS)
H3 (dBFS)
THD (dBFS)
Fclk (MHz)
800
1200
1600
2000
2400
2800
3200
2
2.2
2.4
2.6
2.8
3
3.2
D008
Fin (MHz)
0
2000
4000
6000
8000
10000
7
7.25
7.5
7.75
8
8.25
8.5
8.75
9
D002
BG Calibration
FG Calibration
Fin (MHz)
0
2000
4000
6000
8000
10000
40
45
50
55
60
65
70
75
D129
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
Fin (MHz)
0
2000
4000
6000
8000
10000
7.25
7.5
7.75
8
8.25
8.5
8.75
9
9.25
D132
Fin (MHz)
0
2000
4000
6000
8000
10000
40
45
50
55
60
65
70
75
D131
SNR (dBFS)
SINAD (dBFS)
SFDR (dBFS)
27
ADC12DJ3200
www.ti.com
SLVSD97 – JUNE 2017
Product Folder Links: ADC12DJ3200
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Copyright © 2017, Texas Instruments Incorporated
6.10 Typical Characteristics
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = VD11 = 1.1V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA+/- in single channel modes, fIN = 347 MHz, AIN = -1dBFS, fCLK = maximum rated clock
frequency, filtered, 1-Vpp sine-wave clock, JMODE=1, background calibration, unless otherwise noted. SNR results exclude
DC, HD2 to HD9 and interleaving spurs. SINAD, ENOB and SFDR results exclude DC and fixed frequency interleaving spurs.
JMODE3
FCLK = 3200 MHz
FG Calibration
Figure 4. ENOB vs Input Frequency
JMODE3
FCLK = 3200 MHz
FG Calibration
Figure 5. SNR, SINAD, SFDR vs Input Frequency
JMODE1
FCLK = 3200 MHz
FG+BG Calibration
Figure 6. ENOB vs Input Frequency
JMODE1
FCLK = 3200 MHz
FG Calibration
Figure 7. SNR, SINAD, SFDR vs Input Frequency
JMODE1
FCLK = 3200 MHz
FG Calibration
Figure 8. H2, H3, THD vs Input Frequency
JMODE1
FIN = 347 MHz
FG Calibration
Figure 9. Power Consumption vs Clock Frequency


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