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AD5233 Datasheet(PDF) 3 Page - Analog Devices

Part No. AD5233
Description  Nonvolatile Memory Digital Potentiometers
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5233 Datasheet(HTML) 3 Page - Analog Devices

 
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PRELIMINARY TECHNICAL DATA
AD5231/AD5232/AD5233 - SPECIFICATIONS
REV PrF
3
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS (V
DD = +3V±10% to +5V±10% and VSS=0V,
V
A = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 9)
Clock Cycle Time
t 1
20
ns
Input Clock Pulse Width
t 2 , t 3
Clock level high or low
10
ns
CS Setup Time
t 4
10
ns
Data Setup Time
t 5
From Positive CLK transition
5
ns
Data Hold Time
t 6
From Positive CLK transition
5
ns
CLK Shutdown Time
t 7
0
ns
CS Rise to Clock Rise Setup
t 8
10
ns
CS High Pulse Width
t 9
10
ns
CLK to SDO Propagation Delay10
t 10
RP = 1KΩ, CL < 20pF
1
25
ns
Store to Nonvolatile EEMEM Save Time11
t 12
Applies to Command 2H, 3H, 9H
25
ms
CS to SDO - SPI line acquire
t13
ns
CS to SDO - SPI line release
t14
ns
RDY Rise to
CS Fall
t15
ns
Startup Time
t16
ms
CLK Setup Time
t17
For 1 CLK period (t4 - t3 = 1 CLK period)
ns
Preset Pulse Width (Asynchronous)
tPR
50
ns
Preset Response Time
tPRESP
PR pulsed low then high
70
us
NOTES:
1.
Typicals represent average readings at +25°C and VDD = +5V.
2.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+3V or VDD=+5V.
3.
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
4.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5.
Guaranteed by design and not subject to production test.
6.
Common mode leakage current is a measure of the DC leakage from any terminal A, B, W to a common mode bias level of VDD / 2.
7.
PDISS is calculated from (IDD x VDD) + (ISS X VSS).
8.
All dynamic characteristics use VDD = +5V.
9.
See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching
characteristics are measured using both VDD = +3V or +5V.
10.
Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text.
11.
Low only for instruction commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.12ms; CMD_2,3 ~20ms
12.
Dual Supply Operation primarily affects the POT terminals.
13.
Read Mode current is not continuous.
Timing Diagram
t
2
t
3
MS B
L S B
MS B
L S B
CL K
CS
SD I
SD O
1
t
1
t
4
t
5
t
6
t
7
t
9
t
14
t
10
RDY
t
12
t
17
MS B
L S B
SD O
2
t
13
t
15
t
16
SD O 1 CLK ID LES L O W
SDO 2 CLK ID LES HIG H
t
8
Figure 1. Timing Diagram


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