Si5320
6
Rev. 2.3
Table 2. DC Characteristics, VDD =3.3 V
(VDD33 =3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current 1
IDD
Clock in = 622.08 MHz
Clock out = 19.44 MHz
—
141
155
mA
Supply Current 2
IDD
Clock in = 19.44 MHz
Clock out = 622.08 MHz
—
135
145
mA
Power Dissipation Using 3.3 V Supply
Clock Output
PD
Clock in = 19.44 MHz
Clock out = 622.08 MHz
—
445
479
mW
Common Mode Input Voltage1,2,3
(CLKIN)
VICM
1.0
1.5
2.0
V
Single-Ended Input Voltage2,3,4
(CLKIN)
VIS
See Figure 1A
200
—
5004
mVPP
Differential Input Voltage Swing2,3,4
(CLKIN)
VID
See Figure 1B
200
—
5004
mVPP
Input Impedance
(CLKIN+, CLKIN–)
RIN
—80
—
k
Ω
Differential Output Voltage Swing
(CLKOUT)
VOD
100
Ω Load
Line-to-Line
816
906
1100
mVPP
Output Common Mode Voltage
(CLKOUT)
VOCM
100
Ω Load
Line-to-Line
1.4
1.8
2.2
V
Output Short to GND (CLKOUT)
ISC(–)
–60
—
—
mA
Output Short to VDD25 (CLKOUT)
ISC(+)
—15
—
mA
Input Voltage Low (LVTTL Inputs)
VIL
——
0.8
V
Input Voltage High (LVTTL Inputs)
VIH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
IIL
——
50
µA
Input High Current (LVTTL Inputs)
IIH
——
50
µA
Internal Pulldowns (All LVTTL Inputs)
Ipd
——
50
µA
Input Impedance (LVTTL Inputs)
RIN
50
—
—
k
Ω
Output Voltage Low (LVTTL Outputs)
VOL
IO =.5mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs)
VOH
IO =.5mA
2.0
—
—
V
Notes:
1. The Si5320 device provides weak 1.5 V internal biasing that enables ac-coupled operation.
2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac
coupled to ground.
3. Transmission line termination, when required, must be provided externally.
4. Although the Si5320 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends
maintaining the input clock amplitude below 500 mVPP for optimal performance.
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