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LTC2436-1 Datasheet(PDF) 18 Page - Linear Technology |
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LTC2436-1 Datasheet(HTML) 18 Page - Linear Technology |
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18 / 28 page  LTC2436-1 18 24361f During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the data output state. The data output cycle begins on the first rising edge of SCK and ends after the 19th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 19th rising edge of SCK. After the 19th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. PRESERVING THE CONVERTER ACCURACY The LTC2436-1 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line frequency perturba- tions and so on. Nevertheless, in order to preserve the accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels The LTC2436-1’s digital interface is easy to use. Its digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100 µs.However,someconsiderationsarerequiredtotake advantage of the exceptional accuracy and low supply current of this converter. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state. While a digital input signal is in the range 0.5V to (VCC – 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2436-1 power supply current may increase even if the signal in question is at a valid logic level. For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)]. Figure 11. Internal Serial Clock, Continuous Operation APPLICATIO S I FOR ATIO SDO SCK (INTERNAL) CS LSB MSB SIG CH0/CH1 BIT 2 BIT 1 BIT 0 BIT 14 BIT 13 BIT 15 BIT 16 BIT 17 EOC BIT 18 DATA OUTPUT CONVERSION CONVERSION 24361 F11 VCC FO REF+ SCK CH1+ CH1– SDO GND CS 114 2 3 13 6 7 12 8, 9, 10, 15, 16 11 REFERENCE VOLTAGE 0.1V TO VCC CH0+ CH0– 4 5 ANALOG INPUT RANGE –0.5VREF TO 0.5VREF 1 µF 2.7V TO 5.5V LTC2436-1 2-WIRE INTERFACE REF– = EXTERNAL CLOCK SOURCE = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION |
Similar Part No. - LTC2436-1 |
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Similar Description - LTC2436-1 |
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