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IC41C16105
IC41LV16105
Integrated Circuit Solution Inc.
S2-3
DR014-0A 06/07/2001
TRUTH TABLE
.unction
RAS
RAS
RAS
RAS
RAS
LCAS
LCAS
LCAS
LCAS
LCAS UCAS
UCAS
UCAS
UCAS
UCAS
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Address tR/tC
I/O
Standby
H
H
H
X
X
X
High-Z
Read: Word
L
L
L
H
L
ROW/COL
DOUT
Read: Lower Byte
L
L
H
H
L
ROW/COL
Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write)
L
L
L
L
X
ROW/COL
DIN
Write: Lower Byte (Early Write)
L
L
H
L
X
ROW/COL
Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
Lower Byte, High-Z
Upper Byte, DIN
Read-Write(1,2)
LL
L
H→LL→H
ROW/COL
DOUT, DIN
Hidden Refresh
Read(2) L→H→L
L
L
H
L
ROW/COL
DOUT
Write(1,3) L→H→L
L
L
L
X
ROW/COL
DOUT
RAS-Only Refresh
L
H
H
X
X
ROW/NA
High-Z
CBR Refresh(4)
H→L
L
L
X
X
X
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
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