Electronic Components Datasheet Search |
|
ISPPAC30 Datasheet(PDF) 5 Page - Lattice Semiconductor |
|
ISPPAC30 Datasheet(HTML) 5 Page - Lattice Semiconductor |
5 / 30 page Lattice Semiconductor ispPAC30 Preliminary Data Sheet 5 Pin Descriptions Pins Symbol Name Description PDIP SOIC 15, 16, 17, 18, 25, 26, 27, 28 13, 14, 15, 16, 21, 22, 23, 24 IN Inputs 1, 2, 3, 4 (+ or -) Plus or Minus Differential input pins, with two pins per input (e.g., IN2+ and IN2-). Each are components of VIN, where differential VIN = VIN+ - VIN-. 65 MSEL1 Multiplexer 1 Control Multiplexer logic input pin. Selects either of two analog channels to IA1 (instrument amplifier). Programmable pull-up, pull-down (default), or none. 44 MSEL2 Multiplexer 2 Control Multiplexer logic input pin. Selects either of two analog channels to IA4 (instrument amplifier). Programmable pull-up, pull-down (default), or none. 21, 22 18, 19 OUT Outputs 1 and 2 Single-ended output pins. Internal feedback to inputs accommodated. 20 17 VREFOUT Voltage Reference Output Internal voltage reference output pin (+2.5V nominal). Must be bypassed to GND with a 1µF capacitor. 13 11 ENSPI Enable SPI Mode Enable SPI logic input pin. When high, causes serial port to run in SPI mode. Programmable pull-up or pull-down (default). 12 10 TMS Test Mode Select Serial interface logic mode select pin (input). JTAG interface mode only. Internal pull-up. 11 9 TDO Test Data Out Serial interface logic pin (output) for both JTAG and SPI operation modes. Programmable slew rate, high or low (default). 98 TDI Test Data In Serial interface logic pin (input) for both JTAG and SPI modes. Internal pull-up. 87 TCK Test Clock Serial interface logic clock pin (input) for both JTAG and SPI modes. Programmable pull-up, pull-down (default), or none. 76 CS Chip Select Chip select logic input pin. SPI data transfer enabled by this input. Internal pull-up. 33 CAL Auto-Calibrate Digital pin (input). Commands an auto-calibration sequence on a rising edge. Internal pull-down. 22 PD Power Down Power down enable logic pin (input). Shuts down all power to device. Programmable pull-up (default), pull-down or none. 14 12 VS Supply Voltage Analog supply pin (5V nominal). Should be bypassed to GND with 1µF and .01µF capaci- tors. 11 GND Ground Ground pin. Should normally be connected to the analog ground plane. 23 20 SCOM Signal Common Analog signal common pin (sense). Always con- nected to GND. Auto-calibration accuracy is determined with respect to this pin. 5, 10, 19, 24 — NC No Connects No internal connections are made to these pins in the PDIP package. |
Similar Part No. - ISPPAC30 |
|
Similar Description - ISPPAC30 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |