8 of 46
March 26, 2001
IDT77V012
'
'
'
'H
HH
HYLFH ,QWHUIDFH
YLFH ,QWHUIDFH
YLFH ,QWHUIDFH
YLFH ,QWHUIDFH
The 77V012 uses a UTOPIA level 1 interface to receive and transmit
ATM cells to and from the PHY device. It has a UTOPIA master interface
and operates with a 8-bit data bus. UTOPIA cell level handshake is used
to transfer the cells between the ATM layer and the PHY layer. UTOPIA
byte level handshake is not supported by the 77V012.
The Data Path Interface (DPI) uses a 4-bit data bus, which interfaces
the 77V012 to the IDT SwitchStar.
The EEPROM holds information for initialization and Discovery/Iden-
tify cells. The EEPROM is an option and does not need to be imple-
mented.
The Utility Bus interface contains the control pins used to program
and read the internal PHY registers.
The SRAM interface is used to configure internal registers at reset
and to interface with the external SRAM during normal operation.
The Misc. interface offers two test pins, that are controlled through
registers.
87
87
87
872
2
2
23,$
3,$
3,$
3,$ 5
5
5
5H
HH
HFHL
FHL
FHL
FHLYYYYH
HH
H ,QWHU
,QWHU
,QWHU
,QWHUIIIIDF
DF
DF
DFH
HH
H 2SH
2SH
2SH
2SHUUUUD
DD
DWLRQ
WLRQ
WLRQ
WLRQ
The 77V012 offers a fully compliant UTOPIA Level 1 Receive inter-
face, as specified by the UTOPIA Level 1 specification. The interface is
a UTOPIA master that operates with a 8-bit Input Data Bus
(RxDATA[7:0]). UTOPIA cell level handshake is used to receive ATM
cells from the PHY device. The other signals associated with this inter-
face are Receive Start of Cell (RSOC), Receive Enable (
RENB),
Receive Cell Available (RCLAV), Receive LED (
RxLED), and Receive
Clock (RCLK).
RCLK is a continuous clock, which is half the frequency of System
Clock (SYSCLK).
RxLED indicates if there is activity on the UTOPIA receive bus. This
open drain signal asserts low when a cell is transferred over the bus,
and will stay asserted for 222 RCLK cycles. At 40MHz this is approxi-
mately 0.1 seconds.
The 77V012 will assert
RENB low upon detection of a high RCLAV.
Once RSOC is detected the 77V012 will receive the entire cell without
interruption.
When a TAG is not being used there is no delay between back to
back cells. There is a maximum delay of eight clock cycles between
back to back cells when a four byte TAG is being used.
Figure 2 77V012 Interfaces
DRxFRM
DRxCLK
DRxDATA[3:0]
DTxFRM
DTxCLK
DTxDATA[3:0]
RSOC
RCLK
RxDATA[7:0]
RE NB
RCLAV
TSOC
TCLK
TxDATA[7:0]
TE N B
TCLAV
EEC S
EECLK
SCLK
GW
5347drw04
IDT77V012
EEDOUT
DPI
Receive
Interface
DPI
Transmit
Interface
EEDIN
Serial
EEPROM
Interface
SYSRS T
SYSCLK
System
Interface
ADSP
OE
CE
SRAM
Interface
UTOPIA
Transmit
Interface
UTOPIA
Receive
Interface
ALE
RD
WR
PH YR ST
PHYI NT
AD[7:0]
Utility Bus
Interface
PHYC S
DATA[31:0]
ADDR[17:0]
TxPRTY
CNTRL_A
CNTRL_B
Misc.
Interface
Rx LE D
TxLED