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SMJ320C6413ZTSA400 Datasheet(PDF) 11 Page - Texas Instruments

Part # SMJ320C6413ZTSA400
Description  Fixed-Point Digital Signal Processors
Download  140 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SMJ320C6413ZTSA400 Datasheet(HTML) 11 Page - Texas Instruments

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Features
11
April 2004 − Revised May 2005
SPRS247E
1
Features
D High-Performance Fixed-Point Digital
Signal Processor (TMS320C6413/C6410)
− TMS320C6413
− 2-ns Instruction Cycle Time
− 500-MHz Clock Rate
− 4000 MIPS
− TMS320C6410
− 2.5-ns Instruction Cycle Time
− 400-MHz Clock Rate
− 3200 MIPS
− Eight 32-Bit Instructions/Cycle
− Fully Software-Compatible With C64x™
− Extended Temperature Devices Available
D VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2™ Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Load-Store Architecture With
Non-Aligned Support
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2™ Increased Orthogonality
D VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
D L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache [C6413]
(Flexible RAM/Cache Allocation)
− 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [C6410]
(Flexible RAM/Cache Allocation)
D Endianess: Little Endian, Big Endian
D 32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1024M-Byte Total Addressable External
Memory Space
D Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
D Host-Port Interface (HPI) [32-/16-Bit]
D Two Multichannel Audio Serial Ports
(McASPs) - with Six Serial Data Pins each
D Two Inter-Integrated Circuit (I2C) Buses
− Additional GPIO Capability
D Two Multichannel Buffered Serial Ports
D Three 32-Bit General-Purpose Timers
D Sixteen General-Purpose I/O (GPIO) Pins
D Flexible PLL Clock Generator
D On-Chip Fundamental Oscillator
D IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
D 288-Pin Ball Grid Array (BGA) Packages
(GTS and ZTS Suffixes), 1.0-mm Ball Pitch
D 0.13-µm/6-Level Cu Metal Process (CMOS)
D 3.3-V I/Os, 1.2-V Internal
VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.


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