IDT723623L12 datasheet(1/28 Pages) JGD

Part #	IDT723623L12

Description	CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36

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Manufacturer	JGD [Jinan Gude Electronic Device]

Direct Link	http://www.jgd.com.cn

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2001 Integrated Device Technology, Inc.

DSC-3269/2



AUGUST 2001

CMOS BUS-MATCHING SyncFIFOTM

256 x 36, 512 x 36, 1,024 x 36

IDT723623

IDT723633

IDT723643

COMMERCIAL TEMPERATURE RANGE

IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

.EATURES:

••••• Memory storage capacity:

IDT723623

–

256 x 36

IDT723633

–

512 x 36

IDT723643

–

1,024 x 36

••••• Clocked FIFO buffering data from Port A to Port B

••••• Clock frequencies up to 83 MHz (8 ns access time)

••••• IDT Standard timing (using EF and FF) or First Word Fall

Through Timing (using OR and IR flag functions)

••••• Programmable Almost-Empty and Almost-Full flags; each has

three default offsets (8, 16 and 64)

••••• Serial or parallel programming of partial flags

••••• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

••••• Big- or Little-Endian format for word and byte bus sizes

••••• Reset clears data and configures FIFO, Partial Reset clears data

but retains configuration settings

••••• Mailbox bypass registers for each FIFO

••••• Free-running CLKA and CLKB may be asynchronous or

coincident (simultaneous reading and writing of data on a single

clock edge is permitted)

••••• Easily expandable in width and depth

••••• Auto power down minimizes power dissipation

••••• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

••••• Industrial temperature range (–40

°°°°°C to +85°°°°°C) is available

DESCRIPTION:

TheIDT723623/723633/723643aremonolithic,high-speed,low-power,

CMOS unidirectional Synchronous (clocked) FIFO memories which support

clock frequencies up to 83 MHz and have read access times as fast as 8 ns.

.UNCTIONAL BLOCK DIAGRAM

Mail 1

Register

Programmable Flag

Offset Registers

Status Flag

Logic

EF/OR

AE

36

FF/IR

AF

36

Timing

Mode

FWFT

A0-A35

SPM

FS0/SD

FS1/

SEN

B0-B35

Write

Pointer

Read

Pointer

Mail 2

Register

MBF2

CLKB

CSB

W/RB

ENB

MBB

BE

BM

SIZE

Port-B

Control

Logic

10

3269 drw01

RAM ARRAY

256 x 36

512 x 36

1,024 x 36

CLKA

CSA

W/

RA

ENA

MBA

Port-A

Control

Logic

FIFO1

Mail1,

Mail2,

Reset

Logic

RS1

MBF1

36

PRS

36

RS2

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