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IDT723623 Datasheet(PDF) 5 Page - Jinan Gude Electronic Device

Part # IDT723623
Description  CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36
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Manufacturer  JGD [Jinan Gude Electronic Device]
Direct Link  http://www.jgd.com.cn
Logo JGD - Jinan Gude Electronic Device

IDT723623 Datasheet(HTML) 5 Page - Jinan Gude Electronic Device

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COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
Symbol
Name
I/O
Description
MBF2
Mail2 Register
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2
Flag
register are inhibited while
MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Reset (RS2) or Partial Reset (PRS).
RS1/RS2
Resets
I
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on
RS1selectstheprogrammingmethod(serialorparallel)
and one of three programmable flag default offsets. It also configures Port B for bus size and endian arrangement.
Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
RS1isLOW.
PRS
PartialReset
I
ALOWonthispininitializestheFIFOreadandwritepointerstothefirstlocationofmemoryandsetsthePort Boutput
register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming
method (serial or parallel), and programmable flag settings are all retained.
SIZE(1)
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is
(Port B)
HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement
for Port B. The level of SIZE must be static throughout device operation.
SPM(1)
Serial Program-
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel
ming Mode
programming or default offsets (8, 16, or 64).
W/
RA
Port A Write/
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition
Read Select
of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
RA is HIGH.
W/RB
Port B Write/
I
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition
Read Select
of CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB is LOW.
PIN DESCRIPTIONS (CONTINUED)
NOTE:
1. BM, SIZE and
SPM are not TTL compatible. These inputs should be tied to VCC or GND.


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