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IDT723623 Datasheet(PDF) 21 Page - Jinan Gude Electronic Device

Part # IDT723623
Description  CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36
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Manufacturer  JGD [Jinan Gude Electronic Device]
Direct Link  http://www.jgd.com.cn
Logo JGD - Jinan Gude Electronic Device

IDT723623 Datasheet(HTML) 21 Page - Jinan Gude Electronic Device

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COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, OR is set LOW by the last word or byte read from the FIFO, respectively.
Figure 11. OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
CSA
W/
RA
MBA
IR
A0-A35
CLKB
OR
CSB
W/RB
MBB
ENA
ENB
B0-B35
CLKA
3269 drw12
12
3
tCLKH
tCLKL
tCLK
tENS2
tENS2
tENH
tENH
tDS
tDH
tSKEW1
tCLK
tCLKL
tREF
tREF
tENS2
tENH
tA
Old Data in FIFO Output Register
W1
LOW
HIGH
LOW
HIGH
LOW
tCLKH
W1
HIGH
(1)
FIFO Empty


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