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CY2220 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. CY2220
Description  133-MHz Spread Spectrum Clock Synthesizer/Driver With Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY2220 Datasheet(HTML) 1 Page - Cypress Semiconductor

 
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133-MHz Spread Spectrum Clock Synthesizer/Driver
with Differential CPU Outputs
CY2220
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07206 Rev. *A
Revised December 30, 2002
0
Features
Benefits
• Compliant to Intel® CK00 Clock Synthesizer/Driver
Specifications
Supports next generation Pentium® processors using differen-
tial clock drivers
• Multiple output clocks at different frequencies
— Four pairs of differential CPU outputs, up to 133 MHz
— Ten synchronous PCI clocks
— Two Memory Reference clocks, 180 degrees out of
phase
— Four AGP and Hub Link clocks at 66 MHz
— Two 48-MHz clocks
— Two reference clocks at 14.318 MHz
Motherboard clock generator
— Support Multiple CPUs and a chipset
— Support for PCI slots and chipset
— Drives up to two Direct RambusClock Generators
(DRCG)
— Supports USB host controller and SuperI/O chip
— Supports ISA slots and I/O chip
• Spread Spectrum clocking
— 31 kHz modulation frequency
— Default is –0.6%, which is recommended by Intel
Enables reduction of EMI and overall system cost
• Power-down features
Enables ACPI compliant designs
• Three Select inputs
Supports up to eight CPU clock frequencies
• Low-skew and low-jitter outputs
Meets tight system timing requirements at high frequency
• OE and Test Mode support
Enables ATE and “bed of nails” testing
• 56-pin SSOP package
Widely available, standard package enables lower cost
Intel and Pentium are registered trademarks of Intel Corporation.
Direct Rambus is a trademark of Rambus, Inc.
Logic Block Diagram
EPROM
XTALOUT
XTALIN
14.318
MHz
OSC.
MemRef, MemRefB
SELA
CPU
PLL
REFCLK [0–1]
CPUCLK [0–3]
PCICLK [0–9] (33.33 MHz)
SYS
PLL
USBCLK [0-1] (48 MHz)
MultSel1
MultSel0
SELB
SEL133
CPUCLKB [0–3]
Divider
and
Stop Logic
SPREAD
3V66 [0–3] (66.67 MHz)
SSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
VSSREF
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REFCLK0/MultSel_0
REFCLK1/MultSel_1
VDDREF
25
26
27
28
49
52
51
50
53
56
55
54
VDDPCI
PCICLK_6
Sel133
3V66_1
3V66_2
VSSCPU
CPUCLK_2B
VSSMEM
VSSPCI
PCICLK_5
PCICLK_8
USBCLK1/SelB
AVSS
VDDCPU
CPUCLK_3B
VDDMEM
XTALIN
XTALOUT
PCICLK_0
PCICLK_1
PCICLK_2
PCICLK_3
VSSPCI
PCICLK_4
VDDPCI
PCICLK_7
VSSPCI
PCICLK_9
VDDPCI
VSSUSB
USBCLK0/SelA
VSS3V66
VSS3V66
3V66_3
VDD3V66
AVDD
IREF
CPUCLK_0B
CPUCLK_0
CPUCLK_1B
CPUCLK_1
VSSCPU
CPUCLK_2
VDDCPU
CPUCLK_3
SPREAD
MemRefB
MemRef
VDDUSB
PWR_DWN
3V66_0
VDD3V66
PWR_DWN
Pin Configuration


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