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70T3589S166BCG8 Datasheet(PDF) 12 Page - Integrated Device Technology |
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70T3589S166BCG8 Datasheet(HTML) 12 Page - Integrated Device Technology |
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12 / 28 page  6.42 IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges 12 AC Ele c t ric a l Cha ra c t e rist ic s Ove r t he Ope ra t ing Te m pe ra t ure Ra nge (Re a d a nd Writ e Cyc le T im ing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C) NOTES: 1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when PL/FTX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1) apply when PL/FT = Vss (0V) for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), PL/FT and OPT. PL/FT and OPT should be treated as DC signals, i.e. steady state during operation. 3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port. 4. 166MHz I-Temp is not available in the BF208 package. 5. 200Mhz is not available in the BF208 and DR208 packages. 6. Guaranteed by design (not production tested). 70T3519/99/89 S200 Com'l Only(5) 70T3519/99/89 S166 Com'l & Ind(4) 70T3519/99/89 S133 Com'l & Ind Symbol Parameter Min.Max.Min. Max.Min.Max. Unit tCYC1 Clock Cycle Time (Flow-Through)(1) 15 ____ 20 ____ 25 ____ ns tCYC2 Clock Cycle Time (Pipelined)(1) 5 ____ 6 ____ 7.5 ____ ns tCH1 Clock High Time (Flow-Through)(1) 6 ____ 8 ____ 10 ____ ns tCL1 Clock Low Time (Flow-Through)(1) 6 ____ 8 ____ 10 ____ ns tCH2 Clock High Time (Pipelined)(2) 2 ____ 2.4 ____ 3 ____ ns tCL2 Clock Low Time (Pipelined)(1) 2 ____ 2.4 ____ 3 ____ ns tSA Address Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tSC Chip Enable Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns tHC Chip Enable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tSB Byte Enable Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns tHB Byte Enable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tSW R/W Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns tHW R/W Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tSD Input Data Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns tHD Input Data Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tSAD ADS Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns tHAD ADS Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tSCN CNTEN Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns tHCN CNTEN Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tSRPT REPEAT Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns tHRPT REPEAT Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tOE Output Enable to Data Valid ____ 4.4 ____ 4.4 ____ 4.6 ns tOLZ(6) Output Enable to Output Low-Z 1 ____ 1 ____ 1 ____ ns tOHZ(6) Output Enable to Output High-Z 1 3.4 1 3.6 1 4.2 ns tCD1 Clock to Data Valid (Flow-Through)(1) ____ 10 ____ 12 ____ 15 ns tCD2 Clock to Data Valid (Pipelined)(1) ____ 3.4 ____ 3.6 ____ 4.2 ns tDC Data Output Hold After Clock High 1 ____ 1 ____ 1 ____ ns tCKHZ(6) Clock High to Output High-Z 1 3.4 1 3.6 1 4.2 ns tCKLZ(6) Clock High to Output Low-Z 1 ____ 1 ____ 1 ____ ns tINS Interrupt Flag Set Time ____ 7 ____ 7 ____ 7ns tINR Interrupt Flag Reset Time ____ 7 ____ 7 ____ 7ns tCOLS Collision Flag Set Time ____ 3.4 ____ 3.6 ____ 4.2 ns tCOLR Collision Flag Reset Time ____ 3.4 ____ 3.6 ____ 4.2 ns tZZSC Sleep Mode Set Cycles 2 ____ 2 ____ 2 ____ cycles tZZRC Sleep Mode Recovery Cycles 3 ____ 3 ____ 3 ____ cycles Port-to-Port Delay tCO Clock-to-Clock Offset 4 ____ 5 ____ 6 ____ ns tOFS Clock-to-Clock Offset for Collision Detection Please refer to Collision Detection Timing Table on Page 21 5666 tbl 11 |
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